Semiconductor Memory Channel Structure Impurity Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving optimal channel structure formation and manufacturing methods that allow for precise control of impurity concentration in channel layers for select transistors, which affects threshold voltage control without relying on ion implantation or heat treatment processes.
Innovation Solution
The semiconductor memory device incorporates a gate stacked body with interlayer insulating layers and conductive patterns alternately stacked in a vertical direction, featuring a channel structure that penetrates the gate stacked body, with a core insulating layer and channel layers forming a protruding structure, allowing for the formation of a second channel layer and gate insulating layer to enclose the sidewalls, enabling the adjustment of impurity concentration without ion implantation or heat treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation or heat treatment processes are used to control impurity concentration in channel layers, then threshold voltage control is achieved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent extracts and eliminates the need for ion implantation and heat treatment processes by forming channel structures that protrude from the gate stacked body. This allows impurity concentration control through selective material deposition and structural design rather than post-fabrication modification, thereby reducing manufacturing process complexity while maintaining threshold voltage control precision
Solution Approach 2:
The patent performs preliminary action by pre-forming the channel structure geometry and material composition before final device assembly. The channel layers are formed with appropriate impurity concentrations during the deposition process itself, rather than requiring subsequent ion implantation steps, thus simplifying the overall manufacturing workflow
2Reliability
If channel structures are formed to penetrate the gate stacked body, then select transistor performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the channel structure into distinct portions: a first channel layer forming the main body and a second channel layer forming the protruding portion. This segmentation allows independent optimization and control of each segment's properties, making the overall structure easier to manufacture with standard precision while maintaining the performance benefits of the protruding geometry
Solution Approach 2:
The patent applies local quality by forming the second channel layer with different material composition or impurity concentration specifically at the protruding portion adjacent to the uppermost conductive pattern. This localized modification enhances select transistor performance only where needed, while the rest of the channel structure can be formed with standard manufacturing precision
Data Source
AI summary
Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked in a vertical direction on a substrate, a channel structure penetrating at least a portion of the gate stacked body, and an upper surface of the channel structure left exposed by the gate stacked body.