3D Memory Channel Impurity Segmentation for Reliability
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Solution Overview
Problem
Current three-dimensional nonvolatile memory devices face limitations in operational reliability and integration density, necessitating improved manufacturing methods and structures to enhance performance and efficiency.
Innovation Solution
A semiconductor device with a stack structure of alternately stacked conductive and insulating layers, featuring channel layers with impurity regions of higher impurity concentration than channel regions, and a manufacturing method that includes forming openings and channel layers to optimize memory cell formation and reduce overall resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional nonvolatile memory devices are designed with vertically stacked memory cells to improve integration density, then the degree of integration increases, but operational reliability deteriorates due to increased manufacturing complexity and structural instability
Solution Approach 1:
The channel layer is segmented into multiple regions with different impurity concentrations (first channel region with first impurity concentration, second channel region with second impurity concentration). This segmentation allows different portions of the channel to have optimized electrical properties, improving overall device reliability while maintaining the three-dimensional stacked structure for high integration density.
Solution Approach 2:
Different regions of the channel layer are assigned different impurity concentrations to achieve local optimization of electrical characteristics. The first channel region has a different impurity concentration than the second channel region, allowing each region to contribute differently to device performance, thereby enhancing operational reliability without compromising integration density.
2Ease of manufacture
If conventional manufacturing methods are used for three-dimensional memory devices, then manufacturing processes become increasingly complex, but device performance and efficiency fail to meet consumer demand
Solution Approach 1:
The channel layer is formed with different impurity concentrations in different regions during the initial fabrication process. This preliminary action of creating impurity-doped regions beforehand simplifies subsequent manufacturing steps while ensuring optimal device performance is achieved from the outset, meeting consumer demand without increasing manufacturing complexity.
Solution Approach 2:
The impurity concentration parameter is varied within the channel layer to optimize device performance. By controlling the impurity concentration in different channel regions during manufacturing, the device achieves enhanced electrical characteristics and efficiency without requiring complex multi-step fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the reliability and performance of three-dimensional nonvolatile memory devices by improving channel layer conductivity and memory cell integration, leading to increased cell current and operational efficiency.
Implementation Method 1
a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions
Data Source
AI summary
A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.