Memory Device Channel Layer With Uneven Side Surfaces
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Solution Overview
Problem
As memory devices become more highly integrated, electrons trapped in the charge trap layer of stacked memory cells can escape from the memory cell area, leading to a deterioration in the reliability of the memory device.
Innovation Solution
A memory device with a stacked structure is designed, featuring a channel layer with depressed and protruding side surfaces, a tunnel isolation layer, a charge trap layer, and blocking patterns. The manufacturing method involves forming an opening through alternately stacked material layers, modifying the side surface to an uneven structure, and sequentially depositing the blocking, charge trap, tunnel isolation, and channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are more highly integrated, then storage capacity and density are improved, but electrons trapped in the charge trap layer escape from the memory cell area and reliability deteriorates
Solution Approach 1:
The charge trap layer is segmented into multiple discrete charge trap patterns spaced apart from each other, rather than forming a continuous layer. This segmentation isolates trapped electrons within individual patterns, preventing them from migrating to adjacent memory cell areas and causing reliability issues while maintaining high storage capacity through the stacked structure.
Solution Approach 2:
The channel layer is designed with non-uniform thickness, having a first thickness in a first region and a second thickness in a second region. This local variation in channel layer thickness creates different electric field distributions that confine electrons within specific regions, preventing electron escape while maintaining the overall integrated structure for high storage capacity.
2Ease of manufacture
If a continuous charge trap layer is used, then charge storage is simplified, but electrons escape from memory cell area and reliability deteriorates
Solution Approach 1:
The charge trap layer is divided into multiple separate charge trap patterns rather than forming a continuous layer. This segmentation is achieved through selective removal of the charge trap layer in certain regions, creating discrete patterns that confine electrons locally while still providing effective charge storage functionality.
Solution Approach 2:
Portions of the charge trap layer are extracted or removed to create gaps between charge trap patterns. This extraction prevents electron escape pathways while maintaining sufficient charge storage capacity through the remaining discrete patterns, resolving the contradiction between continuous layer simplicity and electron retention reliability.
3Ease of manufacture
If channel layer has uniform thickness, then manufacturing is simpler, but electron confinement is insufficient and reliability deteriorates
Solution Approach 1:
The channel layer is designed with spatially varying thickness, having a first thickness in a first region and a second thickness in a second region. This local quality variation creates different electric field strengths that effectively confine electrons within the memory cell area, preventing escape while maintaining manufacturability through standard deposition techniques.
Solution Approach 2:
The channel layer thickness is varied in the vertical dimension (thickness direction) rather than changing the horizontal dimensions. This dimensional approach to electron confinement uses thickness variation to create potential wells that trap electrons, providing effective confinement without complicating the lateral structure or manufacturing process.
Data Source
AI summary
A memory device, and a method of manufacturing the same, includes a channel layer enclosing a central axis and extending in a first direction, the channel layer including a side surface depressed toward the central axis and a side surface protruding from the central axis. The memory device also includes a tunnel isolation layer enclosing an outer side surface of the channel layer and a charge trap layer enclosing an outer side surface of the tunnel isolation layer. The memory device further includes charge trap patterns enclosing a depressed portion of the charge trap layer and spaced apart from each other in the first direction. The memory device additionally includes first blocking patterns enclosing a protruding portion of the charge trap layer, second blocking patterns enclosing the charge trap patterns, and gate lines enclosing the second blocking patterns.