Memory Channel Mapping for Reduced Power State Access

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Solution Overview

Problem

Computing devices face challenges in reducing power consumption during reduced power states, as they often require power to access data through multiple memory channels, leading to inefficient battery life and increased design costs.

Innovation Solution

The implementation of a memory manager that proactively maps low-power mode usages to a designated memory channel, allowing other channels to be disabled, thereby reducing power consumption and extending battery life.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If multiple memory channels are used to access data during reduced power states, then data access capability is maintained, but power consumption increases and battery life decreases

Engineering Contradiction:
Improvepower consumptionVSAvoiddata access capability
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent divides the memory system into multiple independent memory channels (first memory channel, second memory channel, third memory channel) that can be independently controlled. During reduced power states, only the first memory channel remains active while the second and third channels are disabled, allowing selective operation of memory segments to reduce power consumption while maintaining necessary data access capability.

Inventive Principle:
Principle #1Segmentation

2Duration of action of moving object

If memory channels are disabled to reduce power consumption, then battery life is extended, but adaptability to different power states is reduced

Engineering Contradiction:
Improvebattery lifeVSAvoidadaptability in reduced power states
Core Design Contradiction:
Duration of action of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic adaptability by allowing the system to transition between different operational configurations based on power state requirements. The memory manager can dynamically enable or disable specific memory channels depending on whether the system is in a reduced power state or full power state, providing versatility across different operating conditions while extending battery life during low-power operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The first memory channel is designed to handle multiple functions independently - it can service both processor cores and functional blocks during reduced power states. This multi-functional capability ensures that disabling the second and third channels does not compromise system functionality, as the first channel can accommodate diverse memory access requirements across different operational modes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of energy

If a memory manager proactively maps low-power mode usages to a designated memory channel, then power waste is reduced, but device complexity increases

Engineering Contradiction:
Improvepower wasteVSAvoidmemory manager complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The memory manager performs preliminary mapping of memory usages to specific memory channels before the system enters reduced power states. By proactively assigning low-power mode block usages to the first memory channel in advance, the system prepares the optimal configuration beforehand, minimizing power waste during transitions while avoiding complex real-time decision-making that would increase operational complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12282378B2Techniques for memory access in a reduced power state
Publication Date: 2025.04.22 INTEL CORP
  • US12282378B2 patent drawing
  • US12282378B2 patent drawing
  • US12282378B2 patent drawing

AI summary

Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.