Semiconductor Memory Channel Pad Segmentation for Probe Contact
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Solution Overview
Problem
The challenge lies in performing stable wafer tests on semiconductor memory devices with small pad sizes and tight pad pitches, as conventional probe cards struggle to maintain contact due to the small dimensions, leading to difficulties in testing and signal measurement.
Innovation Solution
The solution involves a semiconductor memory device with alternating rows of first and second channel pads of larger size and pitch, allowing for selective contact with test probes and enabling lateral or vertical movement for comprehensive testing without incorrect contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the pad size and pad pitch are reduced to decrease chip size, then the chip size is reduced, but the probe needle cannot securely contact the pad and may contact adjacent pads
Solution Approach 1:
The pad structure is segmented into a body pad and an extended pad portion. The extended pad portion protrudes from the body pad in a direction toward the probe needle, creating a dedicated contact region that is spatially separated from the main pad body. This segmentation allows the probe to contact only the extended portion without risking contact with adjacent pads, even when pad pitch is reduced.
Solution Approach 2:
The extended pad portion acts as an intermediary element between the probe needle and the body pad. It provides a dedicated contact interface that mediates the interaction, ensuring reliable electrical contact while preventing direct contact between the probe and adjacent pads. The extended portion serves as a buffer zone that maintains contact reliability in high-density configurations.
2Speed
If the number of input/output data bits is increased to increase system operating speed, then the system operating speed is increased, but it becomes difficult to reduce chip size and fabricate a package
Solution Approach 1:
Instead of increasing chip area horizontally to accommodate more I/O pads, the invention extends pads in the vertical dimension through the extended pad portion. This allows more pads to be packed in the lateral direction without proportionally increasing chip area, as the extended portions utilize the vertical space above the chip surface. This dimensional transition enables higher I/O density while controlling chip footprint.
Solution Approach 2:
The extended pad portions are nested within the overall chip structure, protruding from the chip surface but remaining integrated with the chip body. Multiple extended pads can be arranged in a nested configuration where their contact regions are vertically stacked or closely spaced, allowing high-density I/O connections without proportionally increasing the chip's lateral dimensions.
3Length of moving object
If micro bump technology is used to reduce pad pitch, then pad pitch is reduced, but wafer testing becomes impossible due to probe needle contact errors
Solution Approach 1:
The extended pad portions are formed in advance during the chip fabrication process, before wafer testing is performed. This preliminary structuring ensures that when the wafer is tested with standard probe cards, the extended portions are already in position to provide reliable contact points. The extended structures are pre-positioned to accommodate the probe needle's thickness and positioning error, eliminating the need for special testing procedures.
Data Source
AI summary
Provided are a semiconductor memory device and a test method thereof. The semiconductor memory device includes: a die in which a plurality of internal circuits are integrated; a plurality of first and second channel pads having a first pad size and a first pad pitch, disposed in an alternating manner in a straight line at a center part of the die, and divided into a plurality of parallel rows, wherein the plurality of first and second channel pads are configured to selectively contact test probes in an alternating manner to receive an external wafer test signal and to output a signal generated by the plurality of internal circuits to the exterior. Therefore, it is possible to perform a test using plural channel pads during a wafer test of the semiconductor memory device using a plurality of probes of a probe card without incorrect contacts or non-contact with adjacent pads.