Semiconductor Memory Channel Passivation for Reliability
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Solution Overview
Problem
The challenge in semiconductor memory devices is to improve operation reliability by reducing the area occupied by grain boundaries in polycrystalline silicon channels, which are prone to defects and charge transfer barriers, while maintaining high integration density and electrical performance.
Innovation Solution
The solution involves forming a semiconductor memory device with a channel passivation layer that scales down the thickness of the channel layer in specific regions, reducing surface defects and grain boundary area, and using polycrystalline silicon with increased grain sizes to enhance reliability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polycrystalline silicon channel is used to improve integration density, then device integration is enhanced, but grain boundaries cause defects and charge transfer barriers that reduce reliability
Solution Approach 1:
The patent extracts and removes the harmful grain boundary regions from the channel structure by forming channel holes that extend into the source layer and selectively removing sacrificial layers, thereby eliminating the sources of defects and charge transfer barriers while preserving the polycrystalline silicon channel for high integration density
Solution Approach 2:
The patent applies different structural qualities to different regions: the channel layer in contact with the source layer has improved grain structure with reduced grain boundaries, while maintaining polycrystalline silicon properties in other regions for high integration. This localized quality improvement enhances reliability without sacrificing overall integration density
2Productivity
If channel layer thickness is reduced to improve device performance, then electrical performance is enhanced, but surface defects increase that reduce reliability
Solution Approach 1:
The patent performs preliminary action by forming the channel holes and preparing the channel layer structure before final thickness reduction. The sacrificial layers are positioned and the channel layer is formed with controlled thickness, preventing surface defects from forming in the first place rather than addressing them after thickness reduction
Solution Approach 2:
The patent carefully controls and optimizes the channel layer thickness parameter, forming it to extend into the source layer with specific dimensional relationships. This parameter optimization achieves enhanced electrical performance while maintaining sufficient thickness to minimize surface defects
Data Source
AI summary
A method for fabricating a semiconductor memory device may include the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; and forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region.