3D Memory Channel Passivation for Grain Boundary Reliability
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Solution Overview
Problem
The challenge in semiconductor memory devices is to improve operation reliability, particularly in 3D structures where monocrystalline silicon limitations hinder effective channel formation, and polycrystalline silicon grain boundaries degrade memory cell characteristics.
Innovation Solution
The semiconductor memory device incorporates a channel passivation layer to scale down the thickness of the channel layer and reduce grain boundaries, formed only in specific regions to prevent surface defects and enhance contact characteristics between the source and channel layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon is used for channel formation in 3D structures, then manufacturing complexity is reduced, but grain boundaries degrade memory cell characteristics and operation reliability
Solution Approach 1:
The patent extracts and removes grain boundaries from the channel structure by forming a channel layer without grain boundaries (monocrystalline or epitaxial silicon) instead of using polycrystalline silicon. This extraction eliminates the harmful grain boundary regions that degrade memory cell characteristics while maintaining the 3D vertical channel structure.
Solution Approach 2:
The patent applies different material qualities to different regions: the channel layer is formed with high-quality monocrystalline or epitaxial silicon free of grain boundaries, while the surrounding structures (blockers, tunnel insulators, charge trap layers) maintain their specific local properties. This local quality differentiation ensures optimal performance in the channel region without compromising other structural functions.
2Productivity
If channel layer thickness is reduced to improve device scaling, then integration density increases, but surface defects and thickness variability increase
Solution Approach 1:
The patent introduces a tunnel insulator layer as an intermediary between the channel layer and the blocking insulator. This intermediary layer provides a controlled interface that facilitates precise thickness control of the channel layer while preventing surface defects from propagating. The tunnel insulator acts as a buffer that mediates the interaction between the channel layer and surrounding structures.
Solution Approach 2:
The patent changes the material parameters and formation conditions of the channel layer by using epitaxial silicon growth or selective crystallization processes. These parameter changes enable precise control of channel layer thickness at nanometer scales while maintaining uniformity and reducing surface defects, thereby achieving high integration density without sacrificing manufacturing precision.
3Area of stationary object
If 3D vertical channel structures are implemented to reduce substrate area, then area efficiency improves, but operation reliability decreases due to grain boundary effects
Solution Approach 1:
The patent extracts the harmful grain boundary elements from the vertical channel structure by replacing polycrystalline silicon with monocrystalline or epitaxial silicon. This extraction maintains the 3D vertical architecture for area efficiency while removing the grain boundaries that cause reliability degradation, thereby resolving the contradiction between area occupancy and operation reliability.
Solution Approach 2:
The patent creates a composite structure where the channel layer is formed of high-quality monocrystalline or epitaxial silicon combined with carefully engineered surrounding layers (tunnel insulator, blocking insulator, charge trap layer). This composite material approach maintains the compact 3D vertical structure for area efficiency while the superior crystal quality of the channel layer ensures high operation reliability.
Data Source
AI summary
A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.