3D Memory Channel Pillar Layout for Compact Drain Selection
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration density and operational reliability, particularly in three-dimensional structures, due to misalignment issues and multi-layered structures that increase chip size and reduce performance.
Innovation Solution
A semiconductor memory system with a first structure and a second structure, where the second structure includes a memory device layer with a first stack, a second stack, and a third stack, featuring a channel structure with a first and second channel pillar, where the second channel pillar has a smaller diameter than the first, and is used as a channel for the drain selection transistor, eliminating the need for dummy channels and reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a three-dimensional structure is used to increase integration degree, then the occupying area is reduced, but misalignment issues and multi-layered structures increase chip size and reduce performance
Solution Approach 1:
The device is divided into two separate structures (first structure with source selection line and first channel pillar, second structure with drain selection line and second channel pillar) that are stacked and bonded together. This segmentation allows each structure to be optimized independently while achieving high integration when combined, resolving the contradiction between area reduction and structural complexity.
Solution Approach 2:
The first structure and second structure are stacked one on top of the other with bonding layers in between, creating a nested configuration where each structure contains its own channel pillars and selection lines. This nesting achieves high integration density without requiring complex multi-layered interconnections, as each structure is self-contained.
2Power
If dummy channels are added to ensure sufficient driving capacity, then the driving capacity is improved, but the chip size increases
Solution Approach 1:
The first channel pillar and second channel pillar are merged into a single continuous channel structure that spans both the first and second structures. This unified channel design provides sufficient driving capacity for the drain selection transistor without requiring separate dummy channels, thereby maintaining compact chip size while ensuring adequate power delivery.
Solution Approach 2:
The continuous channel structure serves multiple functions: it acts as the channel for memory cells in the first structure, provides the channel for the drain selection transistor in the second structure, and ensures sufficient driving capacity throughout. This multi-functionality eliminates the need for dedicated dummy channels, reducing chip size while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances integration degree and operational reliability by minimizing chip size in both horizontal and vertical directions, while maintaining sufficient driving capacity through a single-layered structure for the drain selection transistor, thus improving overall performance.
Implementation Method 1
The first bonding layer is hybrid bonded to the second bonding layer
Data Source
AI summary
A semiconductor memory system includes a semiconductor memory device. The semiconductor memory device includes a first stack, a second stack, and a third stack. The second stack is disposed over the first stack. The second stack includes a plurality of word lines stacked and insulated from each other. The third stack is disposed over the second stack. The third stack includes a second selection line. The channel structure includes a first channel pillar formed through the first stack and the second stack, and a second channel pillar contacting the first channel pillar and formed in the third stack. A diameter of the second channel pillar is smaller than a diameter of the first channel pillar.