Semiconductor Memory Device Channel Potential Control
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face challenges in reducing cell size and preventing read disturbance phenomena, where threshold voltages of unselected memory cells change during read, program verify, and erase verify operations due to boosted channel potentials.
Innovation Solution
A semiconductor memory device with memory cell strings and a control circuit that applies specific operating voltages to selection transistors to prevent channel boosting during read and verify operations, using a peripheral circuit to manage voltages and reduce potential levels, thereby suppressing read disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional memory cell strings are used to reduce cell size, then degree of integration is improved, but read disturbance phenomenon occurs due to channel potential boosting
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage levels applied to selection transistors during different operation phases. Specifically, a first voltage level is applied during program/erase operations to allow channel boosting, while a second, lower voltage level is applied during read/verify operations to suppress channel potential boosting and prevent read disturbance. This temporal parameter switching resolves the contradiction between achieving high integration through 3D structures and maintaining threshold voltage stability.
Solution Approach 2:
The invention implements dynamic voltage control where the selection transistor gate voltages are changed based on the operation type. The control circuit switches between different voltage levels (first voltage during program/erase, second voltage during read/verify) to adaptively manage channel potential. This dynamic approach allows the system to achieve both high integration and reliable threshold voltage stability by adjusting operational parameters in real-time.
2Measurement precision
If operating voltage is applied to selection transistors during read operation, then sensing capability is improved, but channel potential increases causing read disturbance in unselected memory cells
Solution Approach 1:
The patent applies local quality by differentiating voltage application between selected and unselected memory cell strings. During read/verify operations, a lower second voltage is applied to selection transistors of unselected strings to prevent channel boosting and read disturbance, while the selected string receives appropriate voltage for sensing. This localized voltage control allows sensing capability to be maintained in the selected cell while protecting unselected cells from read disturbance.
Solution Approach 2:
The invention uses parameter changes by switching voltage levels based on selection status. For unselected memory cell strings during read/verify operations, a second voltage level (lower than the first voltage used during program/erase) is applied to suppress channel potential and prevent read disturbance. This parameter adjustment maintains sensing capability in selected cells while eliminating the harmful effect in unselected cells.
Data Source
AI summary
A semiconductor memory device includes memory cell strings including selection transistors and memory cells coupled between the selection transistors, a peripheral circuit configured to apply an operating voltage to the memory cell strings during a read operation or a verify operation, and a control circuit configured to control the peripheral circuit so that the operating voltage being applied to the selection transistors is controlled to reduce a potential level of a channel of the memory cell strings during the read operation or the verify operation.