Memory Channel Power Management for Sleep State Savings

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Solution Overview

Problem

Current systems consume significant power during system-level sleep states due to the continued operation of physical layer memory channel interfaces and memories in low power modes, leading to reduced battery life and increased heat generation in portable devices.

Innovation Solution

Data is moved from one memory to another, with power being shut off to the original memory and its physical layer interface, while the receiving memory is placed in self-refresh mode, thereby reducing the number of active memory channels and interfaces in low power mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If physical layer memory channel interfaces and memories are kept in low power mode during system sleep state, then system can quickly resume operation, but power consumption increases significantly

Engineering Contradiction:
Improvesystem resume speedVSAvoidpower consumption during sleep state
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides the memory subsystem into multiple independent memory channels, each with its own physical layer interface. During sleep state, the system selectively shuts off power to individual memory channels that do not need to maintain data, while keeping only necessary channels active. This segmentation allows the system to optimize the balance between resume speed and power consumption by activating only the minimal required resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different power management strategies to different memory channels based on their specific requirements. Some channels are completely powered off while others are placed in self-refresh mode, creating localized quality differences in power consumption across the memory subsystem. This allows each memory channel to operate in the most appropriate power state for its current workload.

Inventive Principle:
Principle #3Local quality

2Productivity

If more memory channels are added to support high bandwidth memory, then system performance improves, but power consumption during sleep state increases

Engineering Contradiction:
Improvesystem performanceVSAvoidpower consumption during sleep state
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent treats each memory channel as an independent segment that can be individually managed. When multiple high bandwidth memory channels are present, the system can selectively shut off power to channels that are not currently in use or do not require quick resume capability. This allows the system to maintain high performance capability when needed while dramatically reducing power consumption during sleep states by activating only the essential channels.

Inventive Principle:
Principle #1Segmentation

3Use of energy by moving object

If power is shut off to memory channels during sleep state, then power consumption decreases, but system cannot quickly resume operation

Engineering Contradiction:
Improvepower consumption during sleep stateVSAvoidresume time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent applies differentiated power management to different memory channels based on their specific requirements. Channels that require fast resume capability are kept in self-refresh mode with power maintained, while channels that do not have such requirements are completely powered off. This local quality approach allows the system to minimize overall power consumption while ensuring that critical channels can resume quickly when needed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12260225B2System and method for providing system level sleep state power savings
Publication Date: 2025.03.25 ADVANCED MICRO DEVICES INC
  • US12260225B2 patent drawing
  • US12260225B2 patent drawing
  • US12260225B2 patent drawing

AI summary

A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.