Memory Channel Reconfiguration for Power Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Computer systems using modern DRAMs like GDDR5 face high power consumption due to long wake-up times, making it difficult for memory channels to enter low power modes between requests, which is not efficiently addressed by existing solutions.
Innovation Solution
A circuit and method that reconfigures image data distribution among memory channels and banks, allowing for selective power management by detecting static images and compressing data to enable more channels to enter power save modes, including powering down or reducing voltage and clock frequency of unused channels and banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If modern DRAMs (GDDR5) are used to improve memory access performance, then memory bandwidth and speed are improved, but power consumption increases because channels cannot enter low power modes due to long wake-up times
Solution Approach 1:
The patent divides the memory system into multiple independent memory channels, each capable of being independently controlled and placed in different power states. This segmentation allows the system to activate only the necessary channels for current operations while putting others in low-power mode, resolving the contradiction between maintaining high-speed access capability and reducing overall power consumption.
Solution Approach 2:
The patent dynamically changes operational parameters by adjusting which memory channels are active versus in low-power mode based on workload requirements. This parameter change approach allows the system to optimize between speed and power consumption by adapting the number of active channels to match actual memory bandwidth needs at different times.
2Loss of time
If memory channels are kept active to avoid long wake-up times, then responsiveness is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management where memory channels can transition between active and low-power states based on real-time system demands. This dynamic approach allows channels to remain active when rapid access is needed while entering low-power modes during periods of reduced demand, optimizing the trade-off between wake-up time and power consumption.
Solution Approach 2:
The patent employs periodic monitoring and adjustment of channel power states, transitioning channels between active and low-power modes based on periodic assessment of memory access patterns and system workload, thereby balancing responsiveness with power efficiency over time.
3Reliability
If all memory channels are used for display data to maintain image quality, then display quality is maintained, but power consumption increases
Solution Approach 1:
The patent segments the memory channels used for display data, allowing the system to distribute display traffic across only the necessary subset of channels while keeping other channels in low-power mode. This segmentation maintains required display quality through sufficient bandwidth on active channels while reducing power consumption by minimizing the number of active channels.
Solution Approach 2:
The patent enables memory channels to serve multiple functions - handling both display data and general-purpose memory operations. This multi-functionality allows the system to consolidate workloads onto fewer active channels during display-intensive tasks, maintaining display quality while enabling other channels to enter low-power states.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A circuit includes a memory circuit. The memory retiling circuit moves image information configured to be distributed among a plurality of memory channels into reconfigured image information configured to be distributed among a subset of the plurality of memory channels.