Nonvolatile Memory Channel Reset via Segmented Word Line Voltage
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Solution Overview
Problem
In nonvolatile memory devices, the channel reset operation during bit line precharge increases current consumption and prolongs precharge time due to current drainage through the source select transistor when all memory cells are turned on by the read voltage.
Innovation Solution
The method involves precharging a sense node to precharge a bit line while simultaneously resetting the cell channel by turning off the drain select transistor and turning on the source select transistor, using a first voltage high enough to turn on all memory cells for a time period less than the bit line precharge time, or by resetting the channel to 0V or the precharged bit line voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel reset operation is performed by turning on the source select transistor and applying read voltage to all word lines, then the channel is effectively reset, but current consumption increases and precharge time is prolonged due to current drainage through the source select transistor
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their position. Word lines WL0-WLm receive read voltage Vread to ensure proper channel reset, while word lines WL(m+1)-WL(n-1) receive 0V to prevent current drainage. This localized voltage application maintains channel reset effectiveness in the relevant region while avoiding unnecessary current consumption in other regions.
Solution Approach 2:
The patent divides the word lines into two segments: a first group (WL0-WLm) that receives read voltage for channel reset, and a second group (WL(m+1)-WL(n-1)) that receives 0V to prevent current drainage. This segmentation allows the channel reset function to be performed only where necessary while avoiding harmful current paths.
2Reliability
If the channel reset operation is performed by turning on the source select transistor, then the channel is reset, but the precharge time is prolonged because the precharging cannot start until the source select transistor is turned off
Solution Approach 1:
The patent performs the channel reset operation preliminarily during the bit line precharge phase by applying read voltage to selected word lines while keeping the source select transistor on. This preliminary channel reset action completes before the bit line precharge finishes, eliminating the need to wait for the source select transistor to turn off before starting precharge, thus reducing overall operation time.
Solution Approach 2:
The patent enables continuous operation by maintaining the source select transistor in the on state throughout both the channel reset and bit line precharge operations. This eliminates the idle time where the transistor must turn off and on again, allowing useful actions (channel reset and precharge) to proceed continuously without interruption.
3Reliability
If read voltage is applied to all word lines to turn on all memory cells, then the channel reset is effective, but current drains through the source select transistor to the common source line
Solution Approach 1:
The patent applies read voltage only to specific word lines (WL0-WLm) where channel reset is needed, while applying 0V to other word lines (WL(m+1)-WL(n-1)). This localized voltage application ensures effective channel reset in the target region while preventing current drainage paths through regions where reset is not required.
Solution Approach 2:
The patent segments the word lines into two groups with different voltage assignments. The first group (WL0-WLm) receives read voltage to enable channel reset, while the second group (WL(m+1)-WL(n-1)) receives 0V to block current drainage. This segmentation strategy achieves channel reset efficacy while minimizing energy loss.
Data Source
AI summary
A method of operating a nonvolatile memory device comprising cell strings each comprising memory cells coupled in series between a drain select transistor and a source select transistor, including precharging a sense node to thereby precharge a bit line coupled to the cell string for a program or data read operation; and simultaneously resetting a cell channel in a state in which the drain select transistor is turned off, the source select transistor is turned on, and the memory cells are turned on by applying a first voltage to a number of word lines coupled to the memory cells during a first time period, wherein the first time period is less than a bit line precharge time period.