Non-Volatile Memory Channel Resistance Stabilization
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Solution Overview
Problem
Non-volatile memory devices face errors in read operations due to varying channel resistance between program verification and read operations, leading to decreased read margin and reliability.
Innovation Solution
Incorporating dummy memory cells between selection transistors and memory cells, with specific voltage applications during program verification and read operations to stabilize channel resistance, including applying a verification voltage to selected memory cells and adjusting voltages to dummy memory cells to match read operation conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the same voltage is applied to unselected memory cells during program verification and read operations, then the operation sequence is simplified, but channel resistance varies causing read errors
Solution Approach 1:
The patent applies a specific voltage to dummy memory cells before the read operation to pre-establish the desired resistance state. By setting the dummy memory cells to an erased state before reading, the channel resistance is predetermined to match verification conditions, eliminating read errors caused by resistance variation.
Solution Approach 2:
The patent changes the voltage parameter applied to dummy memory cells between program verification and read operations. During verification, a first voltage is applied to maintain unselected cells in a programmed state, while during read operations, a second voltage is applied to set dummy memory cells in an erased state, thereby controlling channel resistance to ensure accurate reading.
2Reliability
If dummy memory cells are added to stabilize channel resistance, then read margin is improved, but device complexity increases
Solution Approach 1:
The patent introduces dummy memory cells as intermediary elements between the selection transistors and the actual memory cells. These dummy cells act as mediators that control the channel resistance by being set to an erased state before read operations, thereby stabilizing the reading process without requiring fundamental changes to the memory architecture.
3Reliability
If voltage is adjusted to dummy memory cells during read operations, then channel resistance is stabilized, but energy consumption increases
Solution Approach 1:
The patent applies voltage to dummy memory cells periodically - specifically before read operations - rather than continuously. The dummy memory cells are set to an erased state only when needed for reading, and maintain that state until the next read operation, thereby reducing energy consumption compared to continuous voltage application while still stabilizing channel resistance when required.
Data Source
AI summary
A method for operating a non-volatile memory device which includes a plurality of memory cells serially coupled between a source selection transistor and a drain selection transistor, a first dummy memory cell coupled between the source selection transistor and the memory cells, and a second dummy memory cell coupled between the drain selection transistor and the memory cells includes applying a verification voltage to a gate of a selected memory cell, applying a first voltage to gates of unselected memory cells, and applying a second voltage that is lower than the first voltage to a gate of at least one of the first dummy memory cell and the second dummy memory cell, during a program verification operation.