3D Memory Channel Structure With Rounded Plug Corners

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Solution Overview

Problem

Current memory circuitry technologies face challenges in efficiently forming memory arrays with vertically-stacked memory cells, particularly in achieving optimal electrical coupling and structural integrity of channel materials, which affects the performance and reliability of memory cells.

Innovation Solution

The method involves forming a stack with vertically-alternating insulative and conductive tiers, creating channel openings that extend to the conductor tier for direct electrical coupling, and using sacrificial plugs with differential dopant concentrations for diagonal etching, followed by insulator deposition and punch etching to form channel material strings, ensuring precise structural alignment and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertically-stacked memory cells are formed using conventional methods, then memory array structure is achieved, but adverse electric fields at corner regions cause conductivity issues

Engineering Contradiction:
ImproveconductivityVSAvoidadverse electric fields at corner regions
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by modifying only the corner regions of the sacrificial plug with rounded corners, while maintaining the standard structure in other areas. This localized modification reduces adverse electric fields specifically at corner regions where conductivity issues occur, without changing the overall vertically-stacked memory cell structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses preliminary action by forming sacrificial plugs with rounded corners before depositing charge-blocking, storage, and charge-passage materials. This pre-shaping of the sacrificial plug structure ensures that the final memory cell structure has optimized corner regions that reduce adverse electric fields and improve conductivity from the outset.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If vertically-stacked memory cells are formed with optimal electrical coupling, then performance is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveelectrical couplingVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses sacrificial plugs as intermediary structures that facilitate the formation of vertically-stacked memory cells with optimal electrical coupling. These sacrificial plugs are formed with rounded corners to reduce adverse electric fields, and they are later removed to create the final structure. This intermediary approach simplifies the overall manufacturing process compared to directly forming the complex vertically-stacked structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the electrical coupling and structural integrity of memory cells, improving the reliability and performance of memory arrays by ensuring direct and efficient electrical access to memory cells, thereby supporting better data storage and retrieval capabilities.

Implementation Method 1

The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

Insulator material is formed in void spaces left from the removing

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 3

Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings

Methodology Applied
Scientific EffectDirect electrical coupling: Conduction (electrical)

Data Source

PatentUS20230389312A1Memory Circuitry And Method Used In Forming Memory Circuitry
Publication Date: 2023.11.30 MICRON TECHNOLOGY INC
  • US20230389312A1 patent drawing
  • US20230389312A1 patent drawing
  • US20230389312A1 patent drawing

AI summary

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed. Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings. Other embodiments, including structure, are disclosed.