Memory Channel Interfaces with Skewed Slave Clocks
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Solution Overview
Problem
Contemporary memory systems face increased data errors due to higher data input/output speeds, leading to issues like inter-symbol interference and power noise, which affect the reliability of read/write operations.
Innovation Solution
A memory system design that includes multiple channel interfaces and channels, where each channel interface generates a slave clock from an input clock with a different phase, allowing for synchronous communication of control, address, and data signals to memory groups, thereby reducing inter-symbol interference and power noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data I/O speeds are increased to meet contemporary requirements, then productivity is improved, but reliability deteriorates due to increased inter-symbol interference and power noise
Solution Approach 1:
The memory system is divided into multiple independent channel interfaces (first channel interface, second channel interface, etc.), each handling data I/O operations separately with its own slave clock. This segmentation allows parallel data transmission across multiple channels, increasing overall productivity while maintaining reliability through independent error management per channel.
Solution Approach 2:
Different slave clocks with different phases are used to periodically stagger the timing of data operations across channels. This periodic action with phase differences reduces simultaneous switching noise and inter-symbol interference, thereby maintaining reliability at high data I/O speeds.
2Productivity
If multiple channel interfaces operate simultaneously with the same clock phase, then productivity is improved, but harmful factors increase due to inter-symbol interference and power noise
Solution Approach 1:
Each channel interface uses a slave clock with a different phase relative to others, creating asymmetric timing relationships. This asymmetry in clock phases ensures that data operations on different channels do not occur simultaneously, reducing inter-symbol interference and power noise while maintaining high productivity through parallel operations.
3Device complexity
If a single slave clock is used for all channel interfaces, then device complexity is reduced, but reliability deteriorates due to synchronized noise and interference
Solution Approach 1:
Multiple slave clocks are generated from a single master clock source, making the clock generation system universal. Each channel interface independently receives and uses its own phase-adjusted slave clock, maintaining reliability through phase diversity while simplifying the overall system by deriving all clocks from one master source rather than requiring completely independent clock generators.
Data Source
AI summary
A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.