Vertical Channel Memory Structure for Density and Yield Tradeoffs
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Solution Overview
Problem
As design rules of semiconductor devices decrease, there is a need for new technologies to improve integration density and maintain production yield while enhancing resistance and current driving characteristics, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of semiconductor memory devices with vertical channel transistors, featuring bit lines, word lines, and channel patterns with horizontal and vertical portions, along with gate insulating patterns, to enhance integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If design rule is decreased to increase integration density, then integration density is improved, but manufacturing precision and production yield deteriorate
Solution Approach 1:
The channel pattern transitions from a conventional two-dimensional planar structure to a three-dimensional structure with vertical channel portions extending in the third direction perpendicular to the bit line and word line directions. This vertical extension increases the effective channel area without proportionally decreasing the design rule, thereby improving integration density while maintaining manufacturability
Solution Approach 2:
The channel pattern is segmented into multiple portions: horizontal channel portions connected to bit lines, vertical channel portions extending perpendicular to the bit and word lines, and intermediate channel portions connecting these sections. This segmentation allows each portion to be optimized independently for its specific function while maintaining overall manufacturing feasibility
2Area of moving object
If vertical channel transistors are implemented to increase integration density, then integration density is improved, but device complexity increases
Solution Approach 1:
The gate insulating pattern serves multiple functions simultaneously: it provides electrical insulation between the word line and channel pattern, defines the boundary of the channel region, and supports the vertical channel portions. This multi-functionality reduces the need for additional separate structures, thereby managing device complexity while achieving vertical channel transistor implementation
Data Source
AI summary
A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.