Semiconductor Memory Device Charge Circuit Segmentation
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Solution Overview
Problem
Conventional semiconductor memory devices face issues with increased transistor off-leak current due to miniaturization, leading to insufficient charging of dummy bit lines and delayed access, resulting in erroneous readings.
Innovation Solution
The semiconductor memory device incorporates a configuration with multiple bit lines and charge circuits to ensure simultaneous charging of bit lines and source lines, reducing off-leak current and maintaining timing margins by equalizing the charge potential of dummy and normal bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional replica circuit with dummy memory cells is used to control read operation time, then timing control is achieved, but transistor off-leak current increases causing insufficient charging of dummy bit lines and access delays
Solution Approach 1:
The invention divides the bit line charging function into separate charge circuits for different bit line groups. Instead of using a single charge circuit for all bit lines, the patent creates dedicated charge circuits for first bit lines and second bit lines, allowing independent control and optimization of charging for each group, thereby reducing off-leak current impact on timing control
Solution Approach 2:
The patent applies different charging strategies to different bit line groups based on their specific characteristics. First bit lines connected to dummy memory cells receive charging from first charge circuits, while second bit lines receive charging from second charge circuits, allowing each group to be optimized for its specific functional requirements and minimizing the impact of off-leak current
2Area of moving object
If miniaturization is implemented to reduce device size, then integration density increases, but transistor off-leak current increases causing charging insufficient and erroneous readings
Solution Approach 1:
The patent segments the bit line structure into multiple groups with dedicated charge circuits for each group. This segmentation allows the charging current to be distributed more effectively across miniaturized bit lines, compensating for the increased off-leak current that results from device miniaturization and preventing reading errors
Solution Approach 2:
The patent changes the charging parameters by introducing separate charge circuits with optimized charging characteristics for different bit line groups. This allows adjustment of charging current, voltage, and timing parameters to compensate for the increased off-leak current caused by miniaturization, maintaining reading accuracy despite reduced device dimensions
3Duration of action of moving object
If dummy memory cells are used to generate timing signals, then read operation timing is controlled, but off-leak current flows through dummy bit lines causing access delays
Solution Approach 1:
The patent segments the timing control function by separating dummy bit lines into first bit lines (connected to dummy memory cells for timing generation) and second bit lines (for normal operations). Each group has its own dedicated charge circuit, allowing timing signals to be generated without causing access delays in the normal memory operation path
Solution Approach 2:
The patent extracts the timing generation function from the normal memory access path by creating separate dummy memory cell arrays and charge circuits specifically for timing signal generation. This extraction allows timing control to occur independently without interfering with normal memory read operations, eliminating access delays caused by off-leak current in shared bit lines
Data Source
AI summary
In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.