Semiconductor Memory Charge Storage Oxygen Concentration Barrier

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Solution Overview

Problem

Three-dimensionally arranged semiconductor memory devices face reliability issues due to charge loss in the vertical direction, leading to coupling between adjacent memory cells, which decreases the overall reliability of the device.

Innovation Solution

The semiconductor memory device incorporates a charge storage layer with a charge trap portion and a first charge blocking portion, where the oxygen concentration of the first charge blocking portion is higher than that of the charge trap portion, forming an energy barrier to prevent charge loss and reduce coupling between memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but charge loss in the vertical direction occurs leading to coupling between adjacent memory cells and decreased reliability

Engineering Contradiction:
Improvedata storage capacityVSAvoiddevice reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The charge storage layer is segmented into functionally distinct regions: a charge trap portion for storing charge and a first charge blocking portion for preventing vertical charge loss. This segmentation allows each region to perform its specific function optimally, resolving the contradiction between three-dimensional arrangement and charge retention reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the charge storage layer are assigned different oxygen concentrations to create local quality variations. The first charge blocking portion has a higher oxygen concentration than the charge trap portion, creating an energy barrier that prevents charge loss in the vertical direction while maintaining charge storage capability in the trap portion

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If a charge storage layer is formed without oxygen concentration differentiation, then manufacturing process is simplified, but charge loss occurs in the vertical direction causing coupling between memory cells

Engineering Contradiction:
Improvecharge storage layer fabricationVSAvoidcharge loss and coupling
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The oxygen concentration parameter is changed within the charge storage layer to create functional differentiation. By controlling oxygen concentration to be higher in the first charge blocking portion compared to the charge trap portion, an energy barrier is formed that prevents charge loss and coupling between adjacent memory cells

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the reliability of the semiconductor memory device by preventing charge loss in the vertical direction, thereby reducing coupling between adjacent memory cells and improving the device's performance.

Implementation Method 1

an oxygen concentration of the first charge blocking portion is higher than that of the charge trap portion

Methodology Applied
Scientific EffectEnergy barrier formation: Potential Well

Data Source

PatentUS20240357824A1Semiconductor memory device, method for fabricating the same and electronic system including the same
Publication Date: 2024.10.24 SAMSUNG ELECTRONICS CO LTD
  • US20240357824A1 patent drawing
  • US20240357824A1 patent drawing
  • US20240357824A1 patent drawing

AI summary

There is provided a semiconductor memory device having improved reliability. The semiconductor memory device includes a cell substrate, a mold stack including mold insulating layers and gate electrodes, which are alternately stacked on the cell substrate, a semiconductor layer extended in a vertical direction crossing an upper surface of the cell substrate to pass through the mold stack, a blocking insulating pattern between the semiconductor layer and each of the gate electrodes, a charge storage layer including a charge trap portion between the semiconductor layer and the blocking insulating pattern and a first charge blocking portion between the semiconductor layer and each of the mold insulating layers, and a tunnel insulating layer between the semiconductor layer and the charge storage layer, wherein an oxygen concentration of the first charge blocking portion is higher than that of the charge trap portion.