Memory Circuit Word Line Driver With Charge-Sharing Slew Control

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Solution Overview

Problem

Noise-induced voltage changes at cell storage nodes in memory cells can cause bit flipping, leading to SNM failure and deteriorating the integrity of stored bits.

Innovation Solution

A memory circuit design incorporating a word line driver with a conductive line and clamping circuit that suppresses the slew rate of word line transitions through charge sharing, using p-type and n-type diode-connected transistors to mitigate read disturb at storage nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional word line driver is used without charge sharing mechanism, then the word line can be driven with simpler circuitry, but the slew rate of word line transitions is too fast causing read disturb at storage nodes

Engineering Contradiction:
Improvebit integrityVSAvoidword line driver circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A conductive line is introduced as an intermediary element between the word line driver and the memory cell array. This conductive line acts as a charge sharing medium that couples multiple word lines together, enabling controlled charge transfer during word line transitions. The intermediary conductive line allows the driver to maintain simplicity while achieving the desired slew rate control through the physical coupling mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Multiple word lines are merged through their shared connection to the conductive line. During operation, when one word line transitions, the charge is shared with adjacent word lines through the conductive line coupling. This merging approach allows the simple driver circuitry to control multiple word lines simultaneously with controlled slew rates, reducing read disturb while maintaining driver simplicity.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If fast word line transitions are used, then the read operation speed is improved, but the noise-induced voltage change at storage nodes exceeds the static noise margin causing bit flipping

Engineering Contradiction:
Improveread operation speedVSAvoidstatic noise margin
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The charge sharing mechanism operates in a controlled periodic manner during word line transitions. As each word line switches state, the conductive line enables periodic charge transfer to adjacent word lines, creating a controlled sequence of voltage changes. This periodic charge sharing action extends the effective transition time, allowing faster overall read operations while preventing excessive voltage spikes that would compromise the static noise margin.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The conductive line coupling changes the effective electrical parameters of the word line system. By introducing the shared conductive path, the overall capacitance and resistance characteristics are modified, which naturally controls the slew rate of word line transitions. This parameter change allows the system to achieve both fast read operations and adequate noise margins through the physical properties of the conductive line rather than complex active control circuitry.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces read disturb at storage nodes, maintaining bit integrity by minimizing voltage fluctuations and optimizing the static noise margin.

Implementation Method 1

The first conductive line has a length proportional to the number of the word lines. The second electronic component is configured to establish an electrical connection between the word line and the first conductive line in response to a word line enable signal provided from the first electronic component on a first terminal of the second electronic component.

Methodology Applied
Scientific EffectCharge sharing: Capacitance

Implementation Method 2

using p-type and n-type diode-connected transistors to mitigate read disturb at storage nodes

Methodology Applied
Scientific EffectDiode connection: Diode

Data Source

PatentUS12431191B2Memory circuit and word line driver
Publication Date: 2025.09.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12431191B2 patent drawing
  • US12431191B2 patent drawing
  • US12431191B2 patent drawing

AI summary

The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.