Semiconductor Memory Charge Storage Layer Tunneling Current

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Solution Overview

Problem

Current semiconductor memory devices face challenges in maintaining the longevity of memory cells due to tunneling currents and trap level accumulation, which affect the threshold voltage stability and data retention.

Innovation Solution

Incorporating a charge storage layer between the ferroelectric layer and the insulating layer, with the charge storage layer positioned to intercept electrons and reduce tunneling currents, thereby minimizing trap level formation and extending the device's operational life.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional gate insulating layer structure is used, then the device can operate, but tunneling currents occur and trap levels accumulate, degrading threshold voltage stability and data retention over time

Engineering Contradiction:
Improvedata retentionVSAvoidtunneling current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

An insulating layer comprising oxygen (O) and hafnium (Hf) is introduced as an intermediary between the ferroelectric layer and the charge storage layer. This intermediary layer suppresses tunneling currents and reduces trap level accumulation, thereby improving data retention and threshold voltage stability without compromising device operation

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate insulating layer is constructed as a composite structure combining a ferroelectric layer and an insulating layer comprising oxygen and hafnium. This composite structure leverages the dielectric properties of the insulating layer to reduce harmful tunneling currents while maintaining the ferroelectric layer's charge storage capability

Inventive Principle:
Principle #40Composite materials

2Productivity

If the charge storage layer is positioned close to the gate electrode, then data storage efficiency is improved, but tunneling currents increase, accelerating trap level formation and reducing device longevity

Engineering Contradiction:
Improvedata storage efficiencyVSAvoiddevice operational life
Core Design Contradiction:
ProductivityVSDuration of action of stationary object

Solution Approach 1:

The insulating layer comprising oxygen and hafnium serves as a protective intermediary between the charge storage layer and the gate electrode, enabling the charge storage layer to remain positioned for optimal data storage efficiency while the intermediary suppresses tunneling currents that would otherwise accelerate trap level formation and reduce device operational life

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If high voltage is applied to write data, then data storage speed is improved, but tunneling currents increase, causing faster degradation of threshold voltage stability

Engineering Contradiction:
Improvedata storage speedVSAvoidthreshold voltage stability
Core Design Contradiction:
SpeedVSStability of the object's composition

Solution Approach 1:

The insulating layer comprising oxygen and hafnium acts as a protective intermediary that suppresses tunneling currents during high-voltage write operations, enabling fast data storage while preventing the high voltage from causing excessive tunneling that would degrade threshold voltage stability

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces tunneling currents and trap level accumulation, enhancing the stability of threshold voltages and improving data retention in semiconductor memory devices.

Implementation Method 1

Incorporating a charge storage layer between the ferroelectric layer and the insulating layer, with the charge storage layer positioned to intercept electrons and reduce tunneling currents

Methodology Applied
Scientific EffectTunneling current suppression:

Implementation Method 2

the charge storage layer positioned to intercept electrons and reduce tunneling currents, thereby minimizing trap level formation

Methodology Applied
Scientific EffectElectron trapping:

Data Source

PatentUS11903215B2Semiconductor memory device
Publication Date: 2024.02.13 KIOXIA CORP
  • US11903215B2 patent drawing
  • US11903215B2 patent drawing
  • US11903215B2 patent drawing

AI summary

A semiconductor memory device includes: a first semiconductor layer extending in a first direction; a first conductive layer and a second conductive layer that are arranged in the first direction and each opposed to the first semiconductor layer; a first insulating portion disposed between the first semiconductor layer and the first conductive layer, the first insulating portion containing oxygen (O) and hafnium (Hf); a second insulating portion disposed between the first semiconductor layer and the second conductive layer, the second insulating portion containing oxygen (O) and hafnium (Hf); and a first charge storage layer disposed between the first insulating portion and the second insulating portion, the first charge storage layer being spaced from the first conductive layer and the second conductive layer.