Semiconductor Memory Charge Storage Layer Leakage Control
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Solution Overview
Problem
The semiconductor memory device faces issues with threshold voltage control due to leakage currents caused by incomplete charge accumulation in the charge storage layer, leading to unreliable data storage and read operations.
Innovation Solution
The device employs a multi-step write operation sequence, including flash and stripe write operations, to accumulate electric charges in specific regions of the charge storage layer, reducing leakage paths and ensuring accurate threshold voltage control by preliminary charge accumulation in boundary regions before main write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional write operation is used, then the write process is simple and fast, but leakage currents occur due to incomplete charge accumulation in the charge storage layer
Solution Approach 1:
The patent applies preliminary action by performing a first write operation to accumulate charges in boundary regions (inter-string and inter-word line regions) before performing a second write operation for the main data storage region. This preliminary charge accumulation in boundary regions prevents leakage currents during subsequent read operations, thereby improving data storage reliability without significantly increasing overall operation complexity.
2Reliability
If charges are accumulated in all regions including boundary regions, then leakage currents are reduced, but the write operation time increases
Solution Approach 1:
The patent segments the write operation into two distinct phases: a first write operation targeting boundary regions (inter-string and inter-word line regions) and a second write operation targeting the main data storage region. This segmentation allows charges to be accumulated in boundary regions first to prevent leakage, then proceeds to main data writing, thereby maintaining threshold voltage control accuracy while optimizing write operation time by avoiding redundant operations.
Solution Approach 2:
The patent performs preliminary charge accumulation in boundary regions through a first write operation before executing the main data write operation. This preliminary action ensures that boundary regions are properly charged to prevent leakage currents, which improves threshold voltage control accuracy without requiring a complete rewrite of all regions, thus optimizing write operation time.
3Reliability
If a multi-step write operation is implemented, then charge distribution is improved and leakage is reduced, but the operation sequence becomes complex
Solution Approach 1:
The patent segments the operation sequence into a first write operation for boundary regions and a second write operation for the main data region, followed by a read operation. This segmentation clearly defines the purpose and scope of each operation step, making the sequence manageable and systematic. The segmentation improves read operation accuracy by ensuring proper charge distribution while keeping the operation sequence structured and not excessively complex.
Solution Approach 2:
The patent implements a preliminary first write operation to accumulate charges in boundary regions before performing the main second write operation and subsequent read operation. This preliminary action ensures that leakage currents are prevented, thereby improving read operation accuracy. The operation sequence, while multi-step, remains systematic with each step having a clear purpose, avoiding unnecessary complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage currents and ensures reliable data storage by controlling the electric charge distribution in the charge storage layer, enhancing the accuracy of read operations and maintaining the threshold voltage within target values.
Implementation Method 1
accumulate electric charges in specific regions of the charge storage layer
Implementation Method 2
controlling the electric charge distribution in the charge storage layer
Implementation Method 3
a current path between the bit line and the source line via the semiconductor layer
Implementation Method 4
a tunnel insulating layer disposed between the semiconductor layer and the charge storage layer
Data Source
AI summary
A semiconductor memory device includes first conductive layers, second conductive layers, a semiconductor layer disposed between the first conductive layers and the second conductive layers, and a charge storage layer including a first part disposed between the first conductive layers and the semiconductor layer and a second part disposed between the second conductive layers and the semiconductor layer. This semiconductor memory device is configured to execute a first write operation in which a first program voltage is supplied to a third conductive layer which is one of the first conductive layers and a write pass voltage is supplied to a fourth conductive layer which is another of the first conductive layers, and a second write operation in which a second program voltage is supplied to the third conductive layer and to the fourth conductive layer.