3D Memory Charge Storage Segmentation and Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high density and efficient charge storage due to limitations in the design of memory opening fill structures and isolation dielectric pillars, which affect the spacing and contact of discrete charge storage elements.
Innovation Solution
The proposed solution involves a three-dimensional memory device structure with vertically alternating stacks of insulating and conductive layers, featuring memory opening fill structures with a semiconductor channel, tunneling dielectric layer, and discrete silicon nitride portions, along with isolation dielectric pillars, where each pair of discrete silicon nitride portions is vertically spaced and separated by a backside blocking dielectric layer to prevent direct contact, enabling efficient charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If discrete charge storage elements are placed closer together to increase density, then storage capacity improves, but charge isolation and storage efficiency deteriorate
Solution Approach 1:
The charge storage layer is segmented into discrete silicon nitride portions rather than a continuous layer. These discrete portions are vertically spaced apart and separated by backside blocking dielectric layers, creating isolated charge trapping regions that prevent charge leakage while maintaining high density through lateral packing of multiple segments.
Solution Approach 2:
The patent transitions from two-dimensional planar charge storage to three-dimensional vertically stacked discrete portions. By arranging charge storage elements in vertical stacks with lateral spacing and using vertical spacing between pairs, the structure achieves higher density in the vertical dimension while maintaining isolation through the third dimension (depth/backside blocking layers).
2Reliability
If memory opening fill structures are designed with larger spacing to ensure proper charge storage isolation, then charge storage reliability improves, but device density deteriorates
Solution Approach 1:
Multiple functional layers are nested within the memory opening fill structure: semiconductor channel, tunneling dielectric, aluminum oxide liner, and discrete silicon nitride portions are all nested within the same vertical column space. This nesting allows multiple charge storage elements to occupy the same lateral footprint without requiring additional spacing between them.
Solution Approach 2:
Thin dielectric films (tunneling dielectric layer, aluminum oxide liner, backside blocking dielectric layers) are used to provide electrical isolation between discrete silicon nitride portions. These thin films achieve effective charge isolation without requiring large physical spacing between charge storage elements, enabling high density while maintaining reliability.
3Quantity of substance
If discrete silicon nitride portions are arranged in vertical stacks with lateral spacing, then charge storage density improves, but manufacturing complexity increases
Solution Approach 1:
The backside blocking dielectric layers serve multiple functions: they provide electrical isolation between discrete silicon nitride portions, define the vertical spacing between charge storage pairs, and contribute to the overall structural integrity of the memory opening fill structure. This multi-functionality reduces the need for additional specialized components.
Solution Approach 2:
The patent combines multiple charge storage pairs within single memory opening fill structures, and groups multiple such structures between adjacent vertically alternating stacks. By merging multiple functional elements into unified structures, the patent achieves high density while managing complexity through systematic repetition of standardized units.
Data Source
AI summary
Laterally alternating sequences of memory opening fill structures and isolation dielectric pillars are formed between alternating stacks of insulating layers and sacrificial material layers. Each of the memory opening fill structures includes, from inside to outside, a vertical semiconductor channel, a tunneling dielectric layer, and an aluminum oxide liner. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers. Discrete silicon nitride portions are formed on physically exposed surfaces of the aluminum oxide liners employing a selective silicon nitride deposition process, and are employed as charge storage elements. Electrically conductive layers are formed in remaining volumes of the backside recesses. The silicon nitride portions are formed as a pair of discrete silicon nitride portions at each level of the electrically conductive layers within each memory opening fill structure.