Semiconductor Memory Charge Storage Film Upper Cover
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Solution Overview
Problem
The increasing degree of integration in semiconductor memory devices poses challenges in controlling process distribution, affecting their reliability due to the formation of parasitic transistors that can cut off current paths.
Innovation Solution
A semiconductor memory device design featuring a layered structure with gate electrodes, channel structures, and insulating films, including a tunnel insulating film, charge blocking film, and charge storage film, where the charge storage film has an upper cover protruding to control process distribution and prevent parasitic transistor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to enhance device capacity, then productivity and device capability are improved, but process distribution control becomes more difficult and parasitic transistors are formed, worsening reliability
Solution Approach 1:
The gate insulating film is segmented into multiple functional layers: tunnel insulating film, charge storage film, and charge blocking film. This segmentation allows each layer to perform its specific function independently, preventing parasitic transistor formation while maintaining high integration capacity.
Solution Approach 2:
Different regions of the gate insulating film have different properties - the tunnel insulating film region allows controlled tunneling, the charge storage film region stores charges, and the charge blocking film region blocks charge leakage. This local differentiation prevents unwanted parasitic effects while maintaining overall device integration.
2Device complexity
If more semiconductor layers are added to increase integration, then device functionality is enhanced, but process distribution control becomes more difficult, worsening manufacturing precision
Solution Approach 1:
The gate insulating film is divided into three distinct layers with different materials and functions. This segmentation allows for controlled deposition processes where each layer can be formed with precise thickness and composition control, maintaining manufacturing precision even as integration complexity increases.
Solution Approach 2:
The charge storage film acts as an intermediary layer between the tunnel insulating film and the charge blocking film. This intermediate layer facilitates controlled charge transfer and storage while preventing direct interaction between the tunneling region and the blocking region, enabling precise control over the deposition process distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of semiconductor memory devices by reducing the formation of parasitic transistors and improving current path integrity through controlled process distribution.
Implementation Method 1
the gate insulating film including a tunnel insulating film adjacent to the channel layer
Data Source
AI summary
A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.