Memory Check ASIC for Fuzes Ensuring Firmware Integrity

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Solution Overview

Problem

Current explosive devices face challenges in ensuring the integrity of charge-based memory in safety-critical applications, particularly in fuzes and safety and arming (S&A) devices, due to the need for non-reprogrammable logic to prevent accidental detonation, and existing validation methods are inadequate for programmable logic devices.

Innovation Solution

A memory check ASIC is developed to validate the memory contents of microcontrollers in fuzes and S&A devices using a 16-bit cyclic redundancy check (CRC) mechanism, allowing for reprogramming of firmware while maintaining safety standards by ensuring memory integrity through a CRC checker integrated with an external reset circuit and timeout function.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If non-reprogrammable logic is used to ensure memory integrity, then safety and reliability are improved, but adaptability and ease of manufacture deteriorate

Engineering Contradiction:

Improvememory integrityVSAvoidfirmware reprogramming

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The system is divided into two separate components: a reprogrammable microcontroller for firmware and a non-reprogrammable memory check ASIC for validation. This segmentation allows the microcontroller to be updated while the validation logic remains fixed and secure, resolving the contradiction between adaptability and reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The memory check ASIC acts as an intermediary between the microcontroller and the safety functions. It validates the microcontroller's memory contents through CRC checks before allowing execution, serving as a mediator that enables reprogramming while maintaining security through a fixed validation layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If traditional memory validation methods are used, then reliability is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:

Improvememory validationVSAvoidvalidation circuitry

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Complex physical validation circuitry is replaced with a streamlined ASIC that uses cryptographic hash functions (CRC checks) for memory validation. This substitution reduces hardware complexity while maintaining or improving validation reliability through more efficient algorithms.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10490291B1Memory check ASIC for fuzes and safety and arming devices

Publication Date: 2019.11.26 THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY

AI summary

A memory check ASIC for fuzes and safety and arming (S&A) devices. The memory check ASIC may comprise: an ASIC, data line, clock line, shutdown line, and reset line. The ASIC may operatively couple to a microcontroller having a flash-based memory and may comprise: a digital logic for verifying a calculated checksum based on contents of the flash-based memory. A clock signal along with the calculated checksum may be transmitted to the ASIC via the clock line and data line, respectively. A shutdown signal may be transmitted from the ASIC to the microcontroller via the shutdown line in response to the verification of the calculated checksum by the digital logic. A reset signal may synchronize sampling of the calculated checksum and may be latched by flip-flop circuits of the digital logic for a predetermined number of clock cycles.