Memory Check Bit Read Mode for System-Level ECC Visibility
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Solution Overview
Problem
Current memory devices, particularly DRAMs, face increasing errors as manufacturing scales down, and existing error correction methods lack transparency and efficiency in providing error correction information to system-level ECC, potentially exposing sensitive data about the memory device's design and operation.
Innovation Solution
The introduction of a check bit read mode in memory devices allows for the exposure of internal check bits to the host, enabling improved system-level error correction without revealing sensitive information, by generating and storing internal check bits for error correction and providing them to the memory controller upon request, which can be used for system-level RAS improvements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC logic is used to correct single bit failures, then error correction capability is improved, but system-level ECC cannot access error correction information
Solution Approach 1:
The patent extracts the check bits (error correction information) from the internal on-die ECC logic and makes them accessible to system-level ECC through a dedicated read path. This allows system-level ECC to obtain error correction information without accessing the internal correction data directly, resolving the contradiction between maintaining internal ECC functionality and enabling external information access.
Solution Approach 2:
The patent introduces an intermediary mechanism (check bit read mode with mode register) that mediates between the internal on-die ECC logic and system-level ECC. This intermediary allows controlled access to error correction information while protecting sensitive internal correction data, enabling information flow without direct exposure.
2Loss of information
If internal check bits are exposed to system-level ECC, then error correction transparency is improved, but sensitive data about memory device design and operation may be revealed
Solution Approach 1:
The patent extracts only the necessary check bits (error correction information) from the internal ECC logic and exposes them through a controlled interface. This selective extraction provides transparency for error correction purposes while leaving sensitive internal correction data protected, resolving the contradiction between information transparency and data protection.
Solution Approach 2:
The patent introduces a mode register and controlled read path as intermediaries between internal check bits and system-level ECC. This intermediary mechanism enables transparent access to error correction information while preventing direct exposure of sensitive internal correction data, balancing transparency and security requirements.
3Reliability
If check bit read mode is implemented, then system-level RAS capabilities are improved, but device complexity increases
Solution Approach 1:
The patent implements a mode register that provides multi-functionality, allowing the memory device to operate in different modes (normal read mode and check bit read mode). This universal approach enables enhanced RAS capabilities when needed while maintaining standard operation otherwise, minimizing the impact of added complexity by making it conditional and multi-purpose.
Solution Approach 2:
The patent introduces dynamic mode switching capability through a mode register that can be configured to enable or disable check bit read mode. This dynamic approach allows the device to adapt its functionality based on system requirements, providing enhanced RAS capabilities only when configured, thereby managing complexity through conditional activation rather than permanent structural addition.
Data Source
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AI summary
A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one or more read commands for memory devices of the memory subsystem. The read command can include address location information. The memory devices include memory arrays with memory locations addressable with the address location information. The memory locations have associated data and internal check bits, where the check bits are generated internally by the memory for error correction. If the memory device is configured for check bit read mode, in response to the read command, it sends the internal check bits associated with the identified address location. If the memory device is not configured check bit read mode, it returns the data in response to the read command without exposing the internal check bits.