Memory Control Circuit for Check Code Regeneration and Data Accuracy
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Solution Overview
Problem
Existing data accessing methods for rewritable non-volatile memory modules face challenges in ensuring data accuracy during transmission due to potential errors, and the redundant bit area is insufficient to store a large number of check codes, leading to space constraints.
Innovation Solution
A data accessing method and memory controlling circuit unit that utilize multiple check code circuits and an error checking and correcting circuit to generate and verify check codes, ensuring data accuracy while efficiently managing check code storage by regenerating check codes based on data and address information, thereby avoiding redundant bit area limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple check codes are generated and stored to ensure data accuracy, then data reliability is improved, but the redundant bit area becomes insufficient due to space constraints
Solution Approach 1:
The patent applies preliminary action by generating a first check code before data writing and verifying it before reading operations. This pre-verification approach ensures data accuracy is maintained while avoiding the need to store multiple redundant check codes, thus preserving redundant bit area space for other control information.
Solution Approach 2:
The patent changes the parameter of check code verification timing from post-read verification to pre-read verification. By checking data accuracy before the read operation using the first check code, the system maintains high reliability without requiring additional storage space for multiple check codes, effectively resolving the space constraint issue.
2Reliability
If data is verified after reading from memory, then data accuracy is ensured, but transmission time is increased due to re-verification
Solution Approach 1:
The patent performs check code verification before the read operation rather than after. The memory control circuit checks whether the first check code matches the data to be read before initiating the read transmission. This preliminary verification ensures data accuracy while avoiding time loss during actual data transmission, as verification and transmission occur in parallel or verification completes beforehand.
Solution Approach 2:
The patent maintains continuous useful action by overlapping the check code verification process with the data read preparation process. The verification of data accuracy using the first check code occurs concurrently with or immediately before the read operation, ensuring that the data transmission pipeline remains continuously active without interruption for separate verification steps.
3Reliability
If check code verification is performed before reading data, then data accuracy is ensured, but the complexity of the memory control circuit increases
Solution Approach 1:
The patent segments the verification function into a dedicated first check code generation and verification unit within the memory control circuit. This segmentation allows the verification function to be performed before reading without significantly increasing overall circuit complexity, as the verification logic is modular and can be integrated efficiently into the existing memory control architecture.
Solution Approach 2:
The memory control circuit is designed with multi-functionality, where the same circuit components perform both data control operations and check code verification. The first check code circuit is integrated into the existing memory control logic, allowing it to perform verification functions without requiring completely separate dedicated verification hardware, thus minimizing the increase in circuit complexity.
Data Source
AI summary
A data accessing method for a memory storage apparatus is provided. The method includes using a first check code circuit to generate a first check code corresponding to a first data stream and generating a first data set based on the first data stream and the first check code. The method also includes using a second check code circuit to obtain the first data stream and the first check code from the first data set and check the first data stream according to the first check code. The method still includes using a third check code circuit to generate a second check code according to the checked first data stream and generating a data frame based on the checked first data stream and the second check code and thereby programming the data frame into a physical programming unit.