Memory Device Data Pattern Check Unit
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Solution Overview
Problem
Existing memory management systems experience performance deterioration when checking data patterns in non-volatile memory, such as NAND-type flash memory, due to the need for CPU access to Random Access Memory (RAM), which requires multiple memory bus accesses.
Innovation Solution
A memory device and management method that includes a reception unit, read unit, and check unit to receive and process check commands and information within the memory device, allowing data pattern checks without CPU access to RAM, thereby preventing performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data pattern checking is performed by CPU accessing RAM, then data verification can be completed, but system performance deteriorates due to multiple memory bus accesses
Solution Approach 1:
The patent extracts the data pattern checking function from the CPU and moves it to the memory device itself. The memory device includes a check unit that can verify data patterns internally without requiring CPU intervention, thus eliminating the performance bottleneck caused by CPU-RAM memory bus accesses while maintaining data verification capability
Solution Approach 2:
The memory device performs self-verification through its integrated check unit. When data is written to the memory, the check unit automatically checks whether the data pattern matches the expected pattern stored in the control register, enabling the memory device to verify its own data integrity without external CPU assistance
2Productivity
If data is read and checked in the memory device itself, then system performance is maintained, but additional hardware components are required in the memory device
Solution Approach 1:
The check unit in the memory device utilizes the existing read circuitry to perform both data retrieval and pattern verification functions. The same read unit that reads data from memory cells is also used to provide the data to the check unit for pattern matching, thereby achieving multiple functions with minimal additional hardware
Solution Approach 2:
The control register serves as an intermediary component that stores the expected data pattern and facilitates the checking operation. The CPU writes the expected pattern to the control register once, and the check unit uses this stored pattern for verification, eliminating the need for continuous CPU involvement in each check operation
Data Source
AI summary
Disclosed is a memory device which receives a check command and check information from a Central Processing Unit (CPU), reads data written in a predetermined area of a memory based on the check information in response to the check command, and checks a data pattern of the data read based on the check information.