Memory EDC Interface for Check-Bit Transfer Across DM Lines
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Solution Overview
Problem
Existing memory systems face challenges in effectively detecting and correcting errors during data transmission between memory components and controllers, particularly due to limitations in carrying error detection and correction (EDC) bits, especially when using Hamming codes that require more bits than available in a single data unit.
Innovation Solution
The memory system generates and stores EDC bits internally and uses command/address signal lines to supplement the data signal lines, allowing for masked writes where check bits are sent coincident with an asserted data mask signal, ensuring error detection and correction across the communication interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Hamming codes are used for error detection and correction, then error handling capability is improved, but the number of bits required exceeds the capacity of a single data unit
Solution Approach 1:
The patent segments the transmission of EDC bits across multiple channels: data signal lines carry some EDC bits during unmasked writes, while command/address signal lines carry remaining EDC bits. This segmentation allows the complete set of Hamming code bits to be transmitted without exceeding the capacity of any single data unit, resolving the contradiction between error handling capability and bit capacity constraints.
2Adaptability or versatility
If data mask signal lines are used to carry EDC bits, then the existing data transmission infrastructure is utilized, but data transmission capability is reduced when masking is needed
Solution Approach 1:
The patent implements dynamic signal line assignment where the function of data mask signal lines changes based on the operation type: during unmasked writes, these lines carry EDC bits to enhance error detection; during masked writes, they revert to carrying mask signals while EDC bits are transmitted through command/address lines. This dynamic adaptation allows the system to maintain both EDC capability and data transmission capability as needed.
3Reliability
If multiple signal lines are used for EDC bit transmission, then error detection and correction is enhanced, but system complexity increases
Solution Approach 1:
The patent makes existing signal lines multi-functional: data signal lines serve both data transmission and EDC bit transmission roles; command/address signal lines serve both command transmission and supplementary EDC bit transmission roles. This multi-functionality enhances error detection capability without adding dedicated error handling signal lines, thus improving reliability while minimizing the increase in system complexity.
Data Source
AI summary
A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.