On-Chip Memory Checker with Randomized Checksum Validation
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Solution Overview
Problem
Existing memory checking methods for secure memory regions in SoC devices are vulnerable to reverse engineering and side channel attacks due to predictable checksum sequences and accessible checksum values.
Innovation Solution
A memory checker and method that utilize a checksum engine, a result FIFO, and a comparison module to generate and compare checksums with randomized seed values, storing the checksums in an internal FIFO to prevent accessibility and predictability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If checksum values are made accessible for validation, then memory integrity can be verified, but the system becomes vulnerable to reverse engineering and side channel attacks
Solution Approach 1:
The patent extracts the checksum value from the main validation process and stores it separately in a protected location (such as secure memory or fuse). This separation allows the checksum to be used for validation without exposing it to attackers during normal operation. The checksum is taken out of the accessible data path while remaining functional for its intended purpose.
Solution Approach 2:
The patent introduces an intermediary mechanism (such as a protected register or secure storage element) that mediates between the memory validation process and the checksum value. This intermediary allows the checksum to be compared against memory contents without directly exposing the checksum itself, thus maintaining security while enabling validation.
2Ease of operation
If checksum sequences are predictable for validation purposes, then validation logic can be simplified, but security against attacks is reduced
Solution Approach 1:
The patent makes the checksum sequence dynamic rather than static or predictable. This can be achieved by using counter-based indexing, time-varying parameters, or state-dependent selection of which checksum values to validate. The validation logic remains relatively simple but operates on a dynamic sequence that changes with each validation cycle or based on system state.
Solution Approach 2:
The patent changes parameters of the checksum validation process, such as the order in which checksums are validated, the specific checksum values used, or the conditions under which validation occurs. These parameter changes make the validation sequence unpredictable to attackers while maintaining the functional simplicity of the validation logic itself.
Data Source
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AI summary
A method and apparatus for checking the contents of a memory in an integrated circuit is described. The on-chip memory checker includes a result first-in-first-out storage element (FIFO), a checksum engine coupled to the memory, and a comparison module. The method includes the steps of generating a seed value and providing the seed value to the checksum engine. During a test sequence a number of tests are applied to the memory. Each test includes the steps of (i) generating a checksum of a plurality of data values stored in a memory region of the memory by the checksum engine (ii) comparing by the comparison module the checksum with a reference value provided by the result FIFO and (iii) outputting the test result. The checksum is stored in the result FIFO as a reference value for a subsequent test. Multiple test sequences with different (random) seed values may be used.