Non-volatile Memory Device Checkered Cell Allocation
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Solution Overview
Problem
In NAND type flash memory, the narrowing of the programming voltage step-up width to achieve a sharp and narrow threshold distribution is hindered by capacitive coupling from adjacent memory cells, leading to increased programming time and reduced speed, while widening the threshold distribution and reducing integration.
Innovation Solution
The non-volatile semiconductor memory device allocates memory cells with different storage states along bit lines and word lines in a checkered pattern, reducing capacitive coupling effects by programming cells with less data first, which acts as a shield, and using a two-step program verify to control the threshold distribution width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the step-up width of programming voltage Vpgm is narrowed to achieve a sharp threshold distribution, then the threshold distribution becomes narrower, but the number of programming voltage applications increases and programming time becomes longer
Solution Approach 1:
The memory cell array is divided into first and second memory cell arrays with different numbers of storage states. This segmentation allows different programming strategies to be applied to different regions, enabling sharp threshold distribution in critical areas while maintaining faster programming in other areas.
Solution Approach 2:
Adjacent memory cells are configured with different numbers of storage states (first memory cell array with fewer states, second memory cell array with more states). This local differentiation creates a shielding effect where cells with fewer states protect cells with more states from capacitive coupling, allowing narrow threshold distribution without excessive programming iterations.
2Manufacturing precision
If the step-up width of programming voltage Vpgm is narrowed to reduce threshold distribution widening, then interference from adjacent memory cells is reduced, but programming time increases
Solution Approach 1:
Memory cells with fewer storage states are programmed first to establish a stable electrical environment. This preliminary action creates a shielding effect that reduces capacitive coupling interference on subsequent programming of cells with more storage states, allowing narrower step-up width without excessive programming time.
Solution Approach 2:
The memory array uses local differentiation of storage states to create a hierarchical programming structure. Cells are programmed in sequences that exploit their different storage state configurations to minimize mutual interference, reducing both threshold distribution widening and total programming time.
3Quantity of substance
If miniaturization is performed to increase integration, then storage capacity increases, but capacitive coupling between adjacent memory cells becomes significant
Solution Approach 1:
The patent applies local quality by configuring adjacent memory cells with different numbers of storage states. This creates an inherent shielding effect where cells with fewer states act as protective barriers, reducing capacitive coupling interference on cells with more states. This allows miniaturization and increased integration while maintaining signal integrity.
Solution Approach 2:
The patent converts the harmful capacitive coupling effect into a beneficial shielding mechanism. By strategically configuring memory cells with different storage states in adjacent positions, the natural capacitive coupling is transformed into a protective effect that reduces interference on critical cells, enabling higher integration without proportionally increasing interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the impact of capacitive coupling, enhances programming speed, and maintains a sharp threshold distribution, allowing for higher integration and reliability in multi-level data storage.
Implementation Method 1
capacitive coupling of the adjacent cell
Data Source
AI summary
A non-volatile semiconductor memory device includes plurality of word lines and a plurality of bit lines comprising even numbered bit lines and odd numbered bit lines and a memory cell array including a plurality of memory cells having two or more storage states, one of the plurality of memory cells being connected to a corresponding word line of the plurality of word lines, the number of storage states between adjacent memory cells is different in a word line direction and a bit line direction.