Memory System Checkpointing for Sudden Power-Off Recovery
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Solution Overview
Problem
Current memory systems face inefficiencies in interleaving operations across multiple dies, leading to performance degradation and data loss during sudden power-offs due to the need for barrier operations and incomplete programming.
Innovation Solution
A memory system with a controller that includes a check point manager and a recovery manager, which performs check pointing operations by programming essential and dummy check point information across multiple dies, ensuring continuous data patterns for recovery during power failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier operations are performed during interleaving operations across multiple dies, then data consistency is ensured, but performance degradation occurs due to idle times
Solution Approach 1:
The patent applies preliminary action by performing check pointing operations before barrier operations. The controller programs check point information and identification information into memory blocks of multiple dies in advance, creating a ready state that allows barrier operations to be skipped or minimized, thus maintaining data consistency while reducing idle times and improving interleaving performance
2Reliability
If check pointing operations are performed on all dies, then data recovery capability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the check pointing operation into two distinct phases: a first check pointing operation that programs essential check point information and identification information into target dies, and a second check pointing operation that programs dummy check point information and identification information into remaining dies. This segmentation allows the system to maintain data recovery capability while simplifying control logic by clearly separating essential operations from supplementary operations
Data Source
AI summary
A memory system includes a plurality of dies including a plurality of memory blocks, each die including a first region and a second region; and a controller which includes a memory storing plural pieces of check point information and a processor, wherein the processor includes: a check point manager suitable for performing a check pointing operation by programming identification information and check point information on the plurality of memory blocks, according to the size of the plural pieces of; and a recovery manager suitable for resuming an operation stopped due to a sudden power-off (SPO) by using last check point information and last identification information, which are programmed last in memory blocks in each of the dies when the SPO occurs.