Memory Chip Abort Detection via Execution Flags
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Solution Overview
Problem
Power failures during write operations in memory devices, such as NAND flash memory, can cause data corruption or loss due to incomplete programming of bits, leading to corrupted pages with mixed old and new values, which existing technologies struggle to accurately identify and recover from.
Innovation Solution
A memory integrated circuit chip is configured to receive and execute commands, storing indicators such as Program Started Flag (PSF) and Program Ended Flag (PEF) to track the execution status of commands, allowing it to communicate with the memory device controller to determine if a command abort occurred and where in the memory valid or invalid data is located, thereby reducing firmware overhead and facilitating quicker recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power failure occurs during write operation, then data corruption or loss occurs, but existing technologies cannot accurately identify and recover from the corruption
Solution Approach 1:
The patent applies preliminary action by setting execution indicators (PSF and PEF flags) at specific memory locations before and after command execution. These pre-placed markers allow the controller to quickly detect abort conditions by checking whether the flag sequence is complete, eliminating the need for complex post-failure analysis and enabling accurate identification of corrupted data regions.
Solution Approach 2:
The patent introduces execution indicators as intermediary elements between the memory integrated circuit chip and the controller. These indicators act as mediators that carry execution status information from the chip to the controller, enabling the controller to accurately determine whether commands completed successfully without requiring complex communication protocols or additional verification steps.
2Productivity
If traditional methods are used to detect command aborts, then firmware overhead increases and recovery time extends
Solution Approach 1:
The execution indicators are prepared in advance at predetermined memory locations, allowing the controller to immediately detect abort conditions upon power restoration without performing time-consuming analysis. This preliminary preparation of detection markers dramatically reduces mount time and accelerates recovery operations.
Solution Approach 2:
The memory integrated circuit chip automatically maintains the execution indicator flags during normal operation, performing self-monitoring of command execution status. This self-service approach eliminates the need for the controller to implement complex monitoring firmware, reducing firmware overhead and enabling faster detection and recovery from abort conditions.
Data Source
AI summary
Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.