Memory Chip Address Daisy Chain With Delay-Latch Timing
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Solution Overview
Problem
The challenge in constructing large-capacity storage devices is the increase in the number of address pads and bonding wires as the number of memory chips grows, leading to miniaturization difficulties and potential defects in the package.
Innovation Solution
The implementation of a storage device with a controller and memory chips that include address setting circuits, input delay circuits, clock delay circuits, and latches to efficiently set and manage chip addresses, reducing the need for physical address pads and bonding wires through a daisy chain configuration and optimized delay timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory chips is increased to construct large-capacity storage device, then storage capacity is improved, but the number of address pads and bonding wires increases leading to miniaturization difficulties
Solution Approach 1:
The patent merges the address setting function into a shared resource among multiple memory chips. The first memory chip's address setting circuit generates address signals that are sequentially transmitted to subsequent memory chips through daisy-chain connected pads, eliminating the need for separate address pads on each chip. This consolidation reduces the total number of pads required in the package.
Solution Approach 2:
The input pads and output pads serve multiple functions: they are used for normal data input/output operations and also for address signal transmission. The first output pad not only outputs data signals but also transmits the address signal to the second memory chip, enabling pads to perform dual roles and reducing the need for dedicated address pads.
2Quantity of substance
If the number of memory chips is increased to construct large-capacity storage device, then storage capacity is improved, but the number of bonding wires increases leading to potential defects
Solution Approach 1:
The patent combines multiple functions into fewer bonding wires. The same bonding wires that connect input pads and output pads are used for both data signal transmission and address signal transmission. This reduces the total number of bonding wires required, thereby reducing the probability of bonding defects in the package.
3Ease of operation
If direct address assignment is used on address pads of each memory chip, then address identification is simplified, but the number of address pads increases making miniaturization difficult
Solution Approach 1:
The patent segments the address setting function across multiple chips in a sequential manner. The first memory chip performs the address setting operation and generates address signals that are then sequentially transmitted to subsequent chips. This segmentation allows address identification to be distributed across the chip sequence rather than requiring dedicated address pads on each chip.
Solution Approach 2:
The patent introduces an intermediary mechanism where the first memory chip's address setting circuit acts as a mediator that generates and transmits address signals to subsequent chips. This intermediary approach allows address information to be propagated through the system without requiring direct address pads on each chip, thus reducing pad count while maintaining address identification capability.
Data Source
AI summary
A storage device includes a first memory chip including a first input pad configured to receive a first input signal, a first initializing circuit configured to generate a first initializing signal, a first input delay circuit configured to delay the first input signal by a first time to generate a first output signal, a first output pad configured to receive the first output signal and output the first output signal, a first clock delay circuit configured to delay the first initializing signal by a second time to generate a first clock signal, a second clock delay circuit configured to delay the first clock signal by a third time to generate a second clock signal, a first latch configured to store the first input signal based on the first clock signal, and a second latch configured to store the first input signal based on the second clock signal.