Memory Chip Address Remapping for Failed Row Repair

The patent extracts the complex row selection signal switching circuit from the store die and relocates the repair functionality to a separate logic die. By taking out the failed row replacement function from the storage array and implementing it externally through a repair apparatus, the store die can maintain simple circuitry while still achieving reliable failure replacement through the separated logic die that handles address mapping and signal routing.

The patent segments the memory chip into distinct functional components: a store die containing the storage array with simplified circuitry, and a logic die containing the repair apparatus with address mapping logic. This segmentation allows each component to be optimized independently - the store die for storage capacity with minimal circuitry, and the logic die for handling repair operations, thereby reducing overall device complexity while maintaining reliability.

The patent extracts the row selection signal switching functionality from the store die and implements it in a separate logic die. This extraction allows the store die to be minimized to contain only the essential storage array and basic decoding circuitry, while the more complex address mapping and signal switching logic resides in the logic die, thereby reducing the area occupied by the storage apparatus itself.

By segmenting the chip into store die and logic die, the patent allows the store die to be optimized for storage density with minimal overhead circuitry, while the logic die handles the complexity of repair operations. This segmentation enables better area utilization by placing complex logic only where needed, rather than distributing it across the entire storage array area.