Memory Chip Align Circuits Eliminate Serial Parallel Conversion
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Solution Overview
Problem
Current memory systems face challenges in reducing power consumption, access latencies, and die areas while maintaining high bandwidth and data rates, due to the need for serial-to-parallel and parallel-to-serial circuits which increase clock latencies and power consumption.
Innovation Solution
The proposed memory chip design eliminates the need for serial-to-parallel and parallel-to-serial circuits by using align circuits that directly connect memory banks to an I/O data bus, allowing data to be transmitted in parallel without the need for these conversion circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If serial-to-parallel and parallel-to-serial circuits are used to transmit data between memory banks and I/O data bus, then data transmission can be performed, but power consumption increases and access latency increases
Solution Approach 1:
The patent removes the serial-to-parallel and parallel-to-serial conversion circuits from the memory architecture. By extracting these conversion circuits, the patent eliminates the associated power consumption and access latency overhead, allowing data to be transmitted directly in parallel between memory banks and the I/O data bus through align circuits.
Solution Approach 2:
The patent introduces align circuits as intermediary components that directly connect memory banks to the I/O data bus. These align circuits enable parallel data transmission without requiring serial-to-parallel or parallel-to-serial conversion, thereby reducing both power consumption and access latency while maintaining data integrity.
2Area of stationary object
If serial-to-parallel and parallel-to-serial circuits are used for data conversion, then data can be transmitted between different bus widths, but die area increases
Solution Approach 1:
The patent extracts and removes the serial-to-parallel and parallel-to-serial conversion circuits from the memory architecture. This elimination reduces the die area occupied by these conversion circuits while the align circuits provide the necessary adaptability for data transmission between memory banks and the I/O data bus with matching widths.
3Productivity
If wider data bus is used to increase bandwidth, then data transmission rate increases, but power consumption increases and die area increases
Solution Approach 1:
The patent segments the data transmission path into multiple parallel channels through the align circuits. Each align circuit handles a portion of the data in parallel, achieving high bandwidth without requiring a single excessively wide data bus that would consume more power. The segmentation allows efficient utilization of available bus width while controlling power consumption.
4Productivity
If faster data rate is used to transmit data between memory and logic circuit, then bandwidth increases, but cost increases and noise margin decreases
Solution Approach 1:
The patent enables continuous parallel data transmission between memory banks and the I/O data bus without the need for serial-to-parallel or parallel-to-serial conversion stages. This continuous parallel action maintains high data rates while avoiding the noise and timing issues associated with serial conversion, thereby preserving noise margin and reliability.
Data Source
AI summary
A memory chip includes a plurality of memory banks, an I/O data bus, and a plurality of align circuits. Each memory bank outputs or receives a data set in parallel. The plurality of align circuits correspond to the plurality of memory banks respectively. The data set of one memory bank is transferred to one corresponding align circuit which then simultaneously transfers the data set to the I/O data bus in parallel, or the data set is transferred from the I/O data bus to the one corresponding align circuit which then simultaneously transfers the data set to the one memory bank in parallel. There is no parallel-to-serial circuit and serial-to-parallel circuit between the I/O data bus and each memory banks.