Memory Chip Auto-Retry Read Level Adjustment for Faster Testing
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Solution Overview
Problem
Conventional memory chip testing requires expensive test devices to verify responses and change read levels, leading to increased testing time and complexity.
Innovation Solution
The memory chip is equipped with an auto-retry read function that automatically changes the read level and executes retry operations, allowing for simplified testing with inexpensive devices that do not need to verify individual responses from each chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a test device is prepared to detect fail bits and transmit instructions for changing read levels, then the memory chip can be tested for read level accuracy, but the testing cost increases and testing time is extended
Solution Approach 1:
The memory chip automatically detects fail bits in read data and autonomously changes its read level without requiring an external test device to verify responses or transmit control instructions. The chip uses its own circuitry to monitor read operations and adjust read levels based on detected errors, making the testing process self-contained and eliminating the need for complex external verification equipment
Solution Approach 2:
The fail bit detection and read level adjustment functions are extracted from the external test device and integrated directly into the memory chip's internal circuitry. This allows the chip to perform self-testing and self-adjustment, removing the burden of complex verification capabilities from the external test equipment
2Reliability
If the test device verifies responses from the memory chip, then testing accuracy is improved, but the testing time increases
Solution Approach 1:
The memory chip autonomously monitors its own read operations, detects fail bits, and adjusts read levels without requiring external verification. This self-service approach maintains testing reliability through automatic error detection and correction while eliminating the time-consuming back-and-forth communication with external test equipment
Solution Approach 2:
The memory chip proactively changes read levels based on detected fail bits before external verification is needed. By anticipating and correcting errors autonomously, the chip ensures testing accuracy is maintained while reducing the time required for external verification processes
3Productivity
If multiple pages are tested with automatic retry read function, then testing efficiency is improved, but the parameter management complexity increases
Solution Approach 1:
The memory chip automatically manages parameter changes for multiple pages during testing without requiring external intervention. The chip's internal circuitry handles the complexity of tracking and adjusting read levels across multiple pages autonomously, maintaining high testing efficiency while containing parameter management complexity within the chip itself rather than in external test equipment
Data Source
AI summary
According to one embodiment, a memory chip includes a memory cell array and first circuitry. The first circuitry executes a first operation of reading data from a target area of the memory cell array, using a parameter. After the first operation, the first circuitry executes a second operation of changing a set value of the parameter to read the data.