Memory Chip Bank Group Segmentation for Concurrent Data Access
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Solution Overview
Problem
The general memory architecture has low memory data access efficiency and is prone to data access conflicts because each memory chip can only perform reading or writing operations sequentially, leading to inefficiencies when both operations are required simultaneously.
Innovation Solution
The proposed solution involves a memory architecture with multiple memory chips, each having two bank groups and separate read and write amplifiers, allowing for simultaneous reading and writing operations across different bank groups through higher bandwidth input/output buses, enabling independent access and reducing conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If each memory chip includes only one memory bank group with separate read and write amplifiers, then the device complexity is reduced, but the memory data access efficiency deteriorates due to sequential operations
Solution Approach 1:
The memory chip is segmented into two independent memory bank groups (first bank group and second bank group), each with its own read amplifier and write amplifier. This segmentation allows parallel read and write operations to occur simultaneously in different bank groups, resolving the contradiction by enabling concurrent operations while maintaining a relatively simple overall structure.
Solution Approach 2:
The patent introduces a new dimension of parallelism by adding a second bank group that operates independently from the first bank group. This dimensional expansion allows the memory system to perform operations in multiple dimensions simultaneously (read in first bank group, write in second bank group), thereby improving data access efficiency without significantly increasing device complexity.
2Device complexity
If memory chips perform reading and writing operations at different times, then the device complexity is reduced, but the loss of time increases due to sequential execution
Solution Approach 1:
By segmenting the memory chip into two bank groups with separate read and write amplifiers, the patent enables simultaneous execution of read and write operations. This eliminates the sequential time loss while keeping the amplifier configuration relatively simple and manageable.
Solution Approach 2:
The patent ensures continuous useful action by allowing read and write operations to proceed simultaneously in different bank groups rather than alternating between them. This continuity eliminates idle time and maximizes the utilization of memory resources, reducing the overall loss of time.
3Device complexity
If multiple memory chips share the same input/output bus, then the device complexity is reduced, but the bandwidth capacity becomes insufficient for simultaneous operations
Solution Approach 1:
The input/output bus architecture is segmented into multiple independent buses (first input/output bus for read operations, second input/output bus for write operations). This segmentation allows multiple memory chips to transmit data simultaneously through different buses, increasing the total bandwidth capacity while maintaining a relatively simple bus architecture.
Solution Approach 2:
The patent adds dimensional capacity to the bus architecture by introducing separate read and write buses. This multi-dimensional bus structure allows data to flow in multiple directions and channels simultaneously, effectively increasing the quantity of data transmission bandwidth without significantly complicating the overall bus architecture.
Data Source
AI summary
A memory, a memory chip and a memory data access method are provided. The memory of the disclosure includes a plurality of memory chips. Each of the plurality of memory chips includes a first bank group, a second bank group and a read amplifier and a write amplifier. The first bank group includes a plurality of first memory banks. The second bank group includes a plurality of second memory banks. The read amplifier and the write amplifier are separately coupled to the first bank group and the second bank group. The read amplifier and the write amplifier are configured to independently access different bank groups.