Memory Chip Bonding Pad Layout for Word Line Reliability
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing bonding defects, particularly in the word line region where high voltage applications during operations lead to electro migration and potential breaks, due to smaller effective contact areas and tensile stress during annealing.
Innovation Solution
The semiconductor memory device configuration includes a design where the bonding pad in the word line region has a larger length and volume compared to the cell region, increasing the thermal expansion of the conductive material and enhancing the contact area between electrodes, thereby reducing bonding defects and suppressing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the bonding pad size in the word line region is kept small to reduce device complexity, then the device structure remains compact, but bonding defects increase due to electro migration and tensile stress during annealing
Solution Approach 1:
The patent applies local quality by differentiating the bonding pad dimensions between different functional regions. Specifically, the bonding pad in the word line region is designed with a larger area compared to the bonding pad in the cell region. This localized variation in geometry allows the device to maintain overall compactness while providing enhanced bonding reliability in the high-stress word line region where electro migration and tensile stress are most problematic.
2Reliability
If the bonding pad length is increased to reduce bonding defects, then the contact area and thermal expansion increase, but the device area and manufacturing complexity increase
Solution Approach 1:
The invention implements local quality by selectively enlarging only the bonding pad in the word line region while keeping the bonding pad in the cell region at a smaller size. This targeted approach ensures that the increased contact area and thermal expansion benefits are concentrated where they are most needed (in the high-stress word line region) without proportionally increasing the overall device area. The differential sizing optimizes the trade-off between reliability improvement and area overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces bonding defects in the word line region by increasing the contact area and thermal expansion, while maintaining low manufacturing costs and minimizing tensile stress-induced breaks.
Implementation Method 1
increasing the thermal expansion of the conductive material and enhancing the contact area between electrodes
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first chip and a second chip. The first chip includes a plurality of first interconnect layers stacked apart from each other in a first direction, a memory pillar extending in the first direction and passing through the plurality of first interconnect layers, a second interconnect layer electrically coupled to the memory pillar, a first electrode electrically coupled to any one of the plurality of first interconnect layers, and a second electrode electrically coupled to the second interconnect layer. The second chip includes a third electrode bonded to the first electrode, and a fourth electrode bonded to the second electrode. A length of the first electrode in the first direction is larger than a length of the second electrode in the first direction.