3D Memory Chip Bonding With Thick Via Plugs for Misalignment
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Solution Overview
Problem
Existing semiconductor devices, such as three-dimensional memory, face challenges in ensuring proper bonding of metal pads due to misalignment or insufficient expansion during the pasting process.
Innovation Solution
The semiconductor device design includes thicker via plugs and metal pads, with the via plugs being at least twice as thick as the metal pads, and their placement ensures non-overlap in the Z direction to facilitate better expansion and bonding during annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal pads are bonded through a pasting process, then bonding between chips is achieved, but misalignment occurs causing improper bonding
Solution Approach 1:
The via plugs are formed with a thickness that is at least twice that of the metal pads in advance, before the bonding process. This preliminary dimensional preparation ensures that even if misalignment occurs during pasting, the thicker via plugs will still make contact and establish electrical connection, compensating for potential positioning errors.
Solution Approach 2:
The invention changes the dimensional parameter of the via plugs by increasing their thickness to at least twice that of the metal pads. This parameter modification creates a tolerance buffer that accommodates misalignment during bonding, thereby improving bonding reliability without requiring higher manufacturing precision.
2Reliability
If via plugs are made thicker to compensate for misalignment, then bonding reliability improves, but via plug fabrication complexity increases
Solution Approach 1:
The via plugs are made excessively thick relative to the metal pads (at least twice as thick). This excessive dimension in the thickness direction provides a tolerance buffer that compensates for misalignment, improving bonding reliability. The non-overlapping arrangement in the Z direction prevents excessive complexity by maintaining clear spatial separation.
Solution Approach 2:
The invention addresses the alignment problem by transitioning to a three-dimensional solution: making via plugs thicker in the vertical dimension rather than trying to improve horizontal alignment precision. This dimensional change allows the via plugs to accommodate misalignment through their increased thickness while maintaining a relatively simple fabrication process.
3Productivity
If via plugs and metal pads are arranged to non-overlap in Z direction, then bonding efficiency improves, but device volume increases
Solution Approach 1:
The via plugs are segmented into distinct regions: a first region that overlaps with the metal pad in the planar direction, and a second region that extends in the thickness direction without overlapping with other via plugs in the Z direction. This segmentation allows the via plug to fulfill its bonding function while maintaining clear spatial separation from adjacent structures.
Solution Approach 2:
The via plug structure is designed with nested regions where the first region (overlapping with metal pad) is positioned within the vertical projection of the metal pad, while the second region extends upward without interfering with adjacent via plugs. This nested arrangement optimizes space utilization and enables efficient bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the bonding efficiency between the first and second metal pads, reducing resistance and ensuring appropriate bonding even in cases of misalignment, thereby improving the overall performance of the semiconductor device.
Implementation Method 1
their placement ensures non-overlap in the Z direction to facilitate better expansion and bonding during annealing
Implementation Method 2
facilitate better expansion and bonding during annealing
Data Source
AI summary
In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.