Stacked Memory Chip Bonding Layout to Reduce Voids
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing the formation of voids during the bonding process of chips, which can lead to product defects.
Innovation Solution
The semiconductor memory device employs a staggered arrangement of bonding pads on the chips, reducing the coverage area and thereby minimizing the formation of voids during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding pads are arranged in a staggered pattern, then void formation is reduced, but manufacturing complexity increases
Solution Approach 1:
The bonding pads on the first and second chips are arranged in a staggered asymmetric pattern rather than aligned symmetrically. This asymmetric arrangement reduces the coverage area during bonding, minimizing void formation and improving bonding quality while maintaining manufacturability.
2Reliability
If chip coverage area is reduced, then void formation is minimized, but bonding strength may be compromised
Solution Approach 1:
The bonding pads are strategically positioned with different sizes and shapes optimized for their specific locations. The staggered arrangement creates local variations in contact area, ensuring adequate bonding strength in critical regions while minimizing overall coverage to reduce void formation.
Data Source
AI summary
A semiconductor memory device includes first and second chips that are bonded together. The first chip includes a stacked body in which memory cells are formed and first bonding electrodes, and the second chip includes second bonding electrodes. The first bonding electrodes and the second bonding electrodes are joined to each other to form joining electrodes. The stacked body includes an insulating layer that extends in a first direction to separate the stacked body in a second direction. The joining electrodes include first and second joining electrodes, the first joining electrodes being disposed adjacent to a first side of the insulating layer in a third direction, and the second joining electrodes being disposed adjacent to a second side of the insulating layer in the third direction. The first joining electrodes and the second joining electrodes are disposed in a staggered arrangement in the second direction and the third direction.