Memory Chip Clock Phase Shifter for Error-Free Sampling
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Solution Overview
Problem
Conventional methods for synchronizing clock signals with data bits in semiconductor memory devices are time-consuming and require extensive phase shifting to detect error-free sampling points, leading to inefficient data transmission and reception.
Innovation Solution
A memory chip with a receiver, clock phase shifter, error detector, and controller that rapidly identifies error-free sampling points by sequentially shifting the clock signal phase and storing codes corresponding to phases with no errors, allowing for efficient data bit sampling without error detection at each phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the conventional method determines whether each data bit has an error for every phase of the clock signal while shifting the phase, then the data sampling accuracy is improved, but the time required for initial operation becomes excessively long
Solution Approach 1:
The patent segments the data bit verification process by dividing it into two distinct phases: (1) verifying only the first data bit at each clock phase to quickly identify error-free phases, and (2) subsequently verifying remaining data bits only at identified error-free phases. This segmentation avoids the conventional approach of verifying all data bits at every phase, thereby significantly reducing the time required for initial operation while maintaining data sampling accuracy.
2Reliability
If the phase of the clock signal is shifted sequentially to determine error-free sampling points, then the data transmission reliability is improved, but the productivity of data transmission is reduced due to excessive time consumption
Solution Approach 1:
The patent applies preliminary action by first identifying error-free clock phases through quick verification of only the first data bit at each phase, before proceeding to verify remaining data bits. This preliminary identification of suitable phases enables subsequent data transmission to occur at known reliable sampling points, maintaining transmission reliability while reducing the time required for phase calibration and improving overall data transmission efficiency.
Data Source
AI summary
A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n−1) have an error.