Memory Chip Duty Correction Circuit for Parallel Clock Training
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Solution Overview
Problem
Conventional nonvolatile memory devices face performance degradation due to duty mismatch in clock signals, leading to reduced effective data windows and increased DCC training periods, especially as the number of memory chips increases, which affects communication efficiency between nonvolatile memory and controllers.
Innovation Solution
Incorporating a duty correction circuit (DCC) in each memory chip to perform parallel duty correction operations during a dedicated training period, using external clock signals to generate corrected internal clock signals, and employing buffer chips to manage clock signals and data transmission, thereby reducing the overall DCC training period and maintaining performance regardless of the number of memory chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory chips is increased to improve storage capacity, then the storage capacity is improved, but the DCC training period increases and performance degrades
Solution Approach 1:
The system segments the duty correction operation by introducing a dedicated training period during which duty correction is performed, separate from normal operation. This allows parallel processing of duty correction across multiple memory chips without interfering with data transmission, thereby maintaining constant training periods regardless of chip count.
Solution Approach 2:
The duty correction operation is performed preliminarily during a dedicated training period before normal data transmission begins. This preliminary action ensures that duty mismatch is corrected in advance, allowing subsequent high-speed communication to proceed without degradation, regardless of the number of memory chips involved.
2Speed
If the operating frequency is increased to improve communication speed, then the communication speed is improved, but duty mismatch effects are amplified leading to reduced effective data windows
Solution Approach 1:
Duty correction is performed preliminarily during a training period before high-speed communication begins. This advance correction eliminates duty mismatch effects that would otherwise be amplified at high operating frequencies, ensuring reliable effective data windows are maintained throughout high-speed operation.
Solution Approach 2:
The system uses feedback mechanisms where memory chips transmit their duty correction status and the controller adjusts timing parameters based on received signals. This feedback loop ensures that duty mismatch is continuously compensated, maintaining reliable data windows even at elevated operating frequencies.
3Device complexity
If duty correction is performed sequentially across memory chips to simplify control, then the control complexity is reduced, but the overall DCC training period increases
Solution Approach 1:
The training period is segmented into distinct phases where different memory chips perform duty correction in an organized sequence. This segmentation allows for systematic parallel processing while maintaining manageable control complexity through structured timing and coordination protocols.
Solution Approach 2:
The system merges the duty correction operations of multiple memory chips into a unified training period. By coordinating these operations to occur simultaneously rather than sequentially, the overall training period remains constant regardless of the number of chips, while control complexity is managed through centralized coordination.
Data Source
AI summary
Provided is a nonvolatile memory including a clock pin configured to receive an external clock signal during a duty correction circuit training period; a plurality of memory chips configured to perform a duty correction operation on an internal clock signal based on the external clock signal, the plurality of memory chips configured to perform the duty correction operation in parallel during the training period; and an input/output pin commonly connected to the plurality of memory chips, wherein each of the plurality of memory chips includes: a duty correction circuit (DCC) configured to perform the duty correction operation on the internal clock signal; and an output buffer connected between an output terminal of the DCC and the input/output pin.