Memory Chip Data Mover for Flash Endurance
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Solution Overview
Problem
The existing memory hierarchy in computing systems faces challenges in balancing response time, complexity, capacity, and memory bandwidth, particularly in managing data transfer between different types of memory chips, which affects performance and endurance, especially in flash memory devices due to write amplification and limited write cycles.
Innovation Solution
A memory chip with an integrated data mover that facilitates data transfer between memory chips by buffering and bundling data changes, allowing for block access that reduces write frequency and amplification, thereby improving write performance and endurance, and includes encryption and authentication for secure data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data transfer between memory chips is performed with fine-grained granularity, then data access flexibility is improved, but write amplification increases and endurance deteriorates
Solution Approach 1:
The patent segments data transfer operations into two distinct phases: a fine-grained phase for initial data access flexibility, and a block phase for consolidated writing. The data mover circuit divides incoming data into blocks that can be accumulated and transferred together, reducing the frequency of write operations to flash memory while maintaining the ability to access individual bytes when needed.
Solution Approach 2:
The data mover circuit performs preliminary buffering and blocking of data before transfer to secondary memory. By accumulating data in intermediate buffers and preparing blocked transfer units in advance, the system reduces the number of actual write operations to flash memory, thereby reducing write amplification and extending endurance while maintaining data access flexibility.
2Reliability
If data transfer between memory chips is performed frequently, then data synchronization is improved, but write amplification increases and performance deteriorates
Solution Approach 1:
The patent implements periodic block transfer actions where data is accumulated during intervals and then transferred in consolidated blocks. The data mover circuit operates in periodic cycles: accepting fine-grained data requests, accumulating data in buffers, and periodically initiating blocked transfers to secondary memory. This periodic action maintains data synchronization while significantly reducing the frequency of actual write operations to flash memory.
Solution Approach 2:
The data mover circuit maintains continuous useful action by keeping data in intermediate buffers during accumulation phases, rather than performing frequent start-stop transfer operations. The blocking mechanism ensures that data transfer actions are continuous and consolidated, eliminating idle periods and reducing the total number of transfer operations needed to maintain synchronization.
3Reliability
If block access is implemented in data transfer, then write frequency is reduced and endurance is improved, but data access granularity becomes coarser
Solution Approach 1:
The patent implements dynamic data access granularity through the data mover circuit, which can adapt between fine-grained and block access modes based on operational needs. The circuit dynamically buffers individual byte accesses and accumulates them into blocks for transfer, allowing the system to maintain fine-grained access interfaces while physically performing coarser block transfers to flash memory, thus resolving the contradiction between access granularity and endurance.
Data Source
AI summary
A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.