Semiconductor Memory Chip Data Pathway Testing via Dynamic Channel Reconfiguration
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Solution Overview
Problem
Conventional semiconductor apparatuses lack the ability to comprehensively test all circuits, particularly the data transmission/reception unit, during both normal and test operations, which hinders defect verification.
Innovation Solution
A semiconductor apparatus with a memory chip configuration that includes a data input/output block, a data transmission/reception block, and a path selection unit, allowing for selective coupling of channels and a pad based on operation modes, enabling both normal and test data pathways to be utilized for thorough circuit testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor apparatus uses separate data transmission/reception unit and test data transmission/reception unit, then normal operation and test operation can be performed, but the data transmission/reception unit cannot be verified for defects during test operation
Solution Approach 1:
The test data transmission/reception unit is designed to perform dual functions: serving as a dedicated test data interface during test operations and as a normal data transmission/reception unit during normal operations. This multi-functionality allows the same hardware unit to verify defects in the data transmission/reception unit while maintaining normal operational capabilities, thereby improving reliability without proportionally increasing device complexity.
Solution Approach 2:
The test data transmission/reception unit acts as an intermediary that enables indirect verification of the data transmission/reception unit's functionality. By routing test data through this intermediate unit and observing its interaction with the data transmission/reception unit, the system can detect defects without requiring separate dedicated test equipment, thus balancing verification capability with system complexity.
2Productivity
If channels are used for normal data transmission in stacked chips, then integration degree increases and package area reduces, but channels cannot be utilized for testing when chips are not stacked
Solution Approach 1:
The system dynamically adapts the function of the channels based on the operational context. When chips are stacked, the channels function as normal data transmission pathways between chips. When chips are not stacked, the same channels are dynamically reconfigured to serve as test data pathways, allowing defect verification of the data transmission/reception unit. This dynamic adaptability ensures both high integration degree during normal operation and testing flexibility when needed.
Solution Approach 2:
The channels are designed with multi-functionality to serve dual purposes: normal data transmission in stacked chip configurations and test data transmission in non-stacked configurations. This universal design allows the same physical infrastructure to support both high-productivity stacked operations and flexible testing requirements, eliminating the trade-off between integration degree and testing adaptability.
Data Source
AI summary
A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data.