Memory Chip Data Strobe Terminal Testing Method
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Solution Overview
Problem
Existing methods for testing electrical performance parameters of memory chips are hindered by the fact that data strobe signals from memory chip terminals are typically pulse signals, making direct testing challenging and resulting in test blind spots.
Innovation Solution
A method involving controlling the data strobe signal and its complementary signal to maintain specific states during a preset time period, allowing connected driving modules to measure resistance values, thereby enabling effective testing of memory chip electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional test methods are used to test memory chip electrical performance parameters, then the test process can be completed, but the data strobe terminal and complementary data strobe terminal have test blind spots because they output pulse signals that cannot be directly used for testing
Solution Approach 1:
The patent introduces an intermediary measurement process where the data strobe signal and complementary data strobe signal are used to control switching elements, which in turn enable measurement of resistance values through voltage or current signals. This intermediary mechanism bridges the gap between the pulse signals from the data strobe terminals and the measurable electrical parameters, eliminating the test blind spots.
Solution Approach 2:
The patent changes the measurement parameter from directly measuring the pulse signals at the data strobe terminals to measuring resistance values through voltage or current signals. By transforming the measurement approach and using the data strobe signals to control switching states rather than measuring them directly, the patent enables comprehensive testing of all terminals including previously inaccessible data strobe terminals.
2Productivity
If the data strobe terminal and complementary data strobe terminal are used to output pulse signals, then the memory chip can operate, but these signals cannot be directly used to test electrical performance parameters
Solution Approach 1:
The patent makes the data strobe terminal and complementary data strobe terminal multi-functional. These terminals continue to output pulse signals for memory chip operation while simultaneously serving as control signals for switching elements that enable resistance measurement. This universal usage allows the same terminals to fulfill both operational and testing functions without requiring separate dedicated test terminals.
Solution Approach 2:
The patent implements a self-service mechanism where the data strobe signals generated during normal memory chip operation are reused to control the switching elements for resistance measurement. The system uses its own operational signals to facilitate its own testing, eliminating the need for external test signal generation and enabling comprehensive electrical performance testing during normal operation.
3Reliability
If conventional test procedures are applied to memory chips, then testing can be performed, but it is very difficult to test electrical performance parameters due to structural and functional constraints of the memory chip
Solution Approach 1:
The patent introduces dynamic control of switching elements based on the states of data strobe signals and complementary data strobe signals. By dynamically switching between different measurement configurations based on signal states, the system can measure resistance values for different terminals at appropriate times, achieving comprehensive testing without requiring complex simultaneous multi-point measurement hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for accurate measurement of resistance values, effectively addressing the test blind spots and enabling comprehensive testing of memory chip electrical performance with simplicity and low costs.
Implementation Method 1
a first driving module connected to the data strobe terminal is controlled to act and measure a first resistance value, and a second driving module connected to the complementary data strobe terminal is controlled to act and measure a second resistance value
Data Source
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AI summary
The disclosure relates to a method for testing a memory chip, a computer device, and a medium. The method includes: in response to a read command for the memory chip, controlling a clock signal to be kept in a first state within a first preset time period and at the same time controlling a complementary clock signal to be kept in a second state within the first preset time period; in response to the clock signal kept in the first state and the complementary clock signal kept in the second state, keeping a data strobe signal in the first state within a second preset time period and at the same time keeping a complementary data strobe signal in the second state within the second preset time period; and when the data strobe signal is kept in the first state and the complementary data strobe signal is kept in the second state, controlling a first driving module connected to a data strobe terminal to operate and measure a first resistance value and controlling a second driving module connected to a complementary data strobe terminal to operate and measure a second resistance value. The test method in the disclosure is simple and has low costs and an adequate test effect.