Memory Chip Direct Data Transfer via Phase Adjustment
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing data transfer between memory chips and a controller, particularly in operations like inter-chip and inter-plane copy operations, which can be hindered by the need for intervention from the controller.
Innovation Solution
The memory system incorporates a controller and multiple memory chips, each with a memory cell array, phase adjustment circuit, and control circuit. This configuration allows for direct data transfer between memory chips without controller intervention, utilizing phase adjustment circuits to synchronize data and timing signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data transfer between memory chips goes through the controller, then the controller can manage data transfer, but the time required for data copy operations increases
Solution Approach 1:
The patent divides the data transfer function into two segments: controller-managed transfer (for simplicity) and direct memory-to-memory transfer (for performance). By segmenting the data transfer paths, the system can choose the appropriate path based on operational requirements, resolving the contradiction between transfer time and control complexity.
Solution Approach 2:
The patent introduces an intermediary mechanism (direct transfer capability) that allows memory chips to communicate without the controller as an intermediary. This intermediary path exists alongside the traditional controller-mediated path, enabling the system to bypass controller intervention when speed is critical, thus reducing transfer time without eliminating control functionality.
2Productivity
If direct data transfer between memory chips is enabled, then data copy speed increases, but the need for phase adjustment circuits increases device complexity
Solution Approach 1:
The patent applies local quality by implementing phase adjustment circuits only at specific locations (memory chip interfaces) rather than throughout the entire system. The phase adjustment is localized to where it is most needed - at the boundaries where direct memory-to-memory transfer occurs - thereby enabling high-speed transfer without proportionally increasing overall system complexity.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the phase of timing signals based on the operational mode (direct transfer vs. controller-mediated transfer). The phase adjustment circuit modifies timing parameters only when direct transfer is active, allowing the system to optimize data copy speed without permanently increasing complexity in all operational states.
3Ease of operation
If controller-mediated data transfer is used, then data transfer control is simplified, but system efficiency decreases
Solution Approach 1:
The patent implements a dynamic data transfer control mechanism that can switch between controller-mediated and direct transfer modes based on system state and operational requirements. This dynamic adaptability allows the system to maintain simplicity in normal operations while achieving high efficiency when needed, resolving the contradiction between ease of operation and productivity.
Solution Approach 2:
The patent creates a universal data transfer system that can handle multiple functions through a single architecture: the same memory chip interface can support both controller-mediated transfer (for simplicity and compatibility) and direct transfer (for efficiency and speed). This multi-functionality allows the system to adapt to different operational needs without requiring separate dedicated paths for each mode.
Data Source
AI summary
A memory system includes first and second memory chips, each including first and second pads, a phase adjustment circuit, and a control circuit. The first pads of the memory chips are commonly connected and the second pads of the memory chips are commonly connected. In response to a first command set for the first memory chip to read data and a second command set for the second memory chip to write data, the control circuit of the first memory chip reads and outputs a data signal through its first pad along with a timing signal output through its second pad, and concurrently therewith, the control circuit of the second memory chip receives the data through its first pad with reference to a timing signal received through its second pad and writes the data thereinto.