Memory Chip Duty Ratio Calibration During Parallel Readout

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Solution Overview

Problem

Existing semiconductor storage devices and memory systems face challenges in calibrating output signals due to variations in duty ratio after power supply activation, which can affect performance and require additional circuitry like PLL or DLL, potentially impacting design and efficiency.

Innovation Solution

The implementation of a duty ratio calibration mechanism within the memory system that allows for parallel calibration with read operations, using a correction circuit and detection circuit to adjust output signals based on detected duty ratio deviations, without the need for additional circuits like PLL or DLL.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If additional circuits like PLL or DLL are used to calibrate duty ratio, then calibration precision is improved, but device complexity increases

Engineering Contradiction:

Improveduty ratio calibration precisionVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the duty ratio calibration function from complex PLL/DLL circuits and implements it using a simplified detection circuit and correction circuit. The detection circuit measures the duty ratio of read signals, and the correction circuit adjusts the output signal timing based on detected deviations, achieving calibration without requiring complex phase-locked or delay-locked loop circuits.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The memory device performs self-calibration of its output signals using internally generated detection and correction circuits. The system automatically detects duty ratio deviations in read signals and corrects output signal timing without external intervention or complex calibration hardware, enabling the device to maintain its own signal integrity.

Inventive Principle:

Principle #25Self-service

2Measurement precision

If calibration operation is executed independently of read operations, then calibration precision is improved, but productivity decreases

Engineering Contradiction:

Improvecalibration accuracyVSAvoidoperation efficiency

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent merges the calibration operation with the read operation by executing duty ratio detection and correction during the read process. The detection circuit operates concurrently with read signal transmission, and corrections are applied in real-time without pausing or separating calibration from normal memory operations, thereby maintaining both accuracy and efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The calibration process continues uninterrupted during read operations rather than being executed as a separate preliminary step. The detection circuit continuously monitors duty ratio deviations in read signals and the correction circuit continuously adjusts output timing, ensuring uninterrupted calibration coverage throughout normal memory operations.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11177008B2Semiconductor storage device and memory system in which control circuit of the semiconductor storage device executes calibration operation according to timing at which data is read from another semiconductor storage device

Publication Date: 2021.11.16 KIOXIA CORP

AI summary

A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.