Memory Chip Dual-Loop Clock Training for Phase and Duty Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing storage devices face challenges in aligning phases of signals and reducing signal duty cycle degradation, particularly as communication between nonvolatile memories and controllers requires higher operating frequencies.
Innovation Solution
The proposed memory device includes a clock pin/pad and a memory chip with first and second loop circuits. The first loop circuit performs phase calibration by detecting phase differences between signals and generating delay signals. The second loop circuit performs duty cycle correction by comparing duty cycles of reverse signals and generating control signals for duty cycle adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If communication frequency between nonvolatile memories and controllers is increased, then productivity is improved, but signal phase alignment and duty cycle accuracy deteriorate
Solution Approach 1:
The patent implements a training section before normal communication operations where phase calibration and duty cycle correction are performed in advance. The phase detector and delay cell adjust signal phases preliminarily, while the duty cycle correction circuit optimizes duty cycles before high-speed communication begins, ensuring reliable signal alignment at higher frequencies
Solution Approach 2:
The patent employs feedback mechanisms where the phase detector continuously monitors phase differences between signals and adjusts timing through delay cells. The duty cycle correction circuit also uses feedback to detect and correct duty cycle deviations, maintaining signal integrity during high-frequency operations by continuously adapting to signal variations
2Productivity
If communication frequency between nonvolatile memories and controllers is increased, then productivity is improved, but signal duty cycle accuracy deteriorates
Solution Approach 1:
The duty cycle correction circuit performs duty cycle optimization during the training section before high-speed communication begins. By preliminarily adjusting duty cycles to desired levels, the system ensures accurate signal timing is established before productivity-critical operations commence
Solution Approach 2:
The duty cycle correction circuit continuously monitors duty cycle deviations through phase detection and applies corrective adjustments. This feedback mechanism maintains duty cycle accuracy during high-frequency operations by detecting deviations and automatically compensating for them in real-time
3Measurement precision
If phase calibration and duty correction operations are implemented, then signal alignment accuracy is improved, but device complexity increases
Solution Approach 1:
The patent combines the phase detector with both the delay cell for phase calibration and the duty cycle correction circuit in an integrated architecture. By merging these functions into a unified training section, the system achieves accurate phase and duty cycle control while reducing overall device complexity through functional integration rather than separate independent circuits
Data Source
AI summary
A memory chip performs phase calibration and duty cycle correction operations using first and second loop circuits. The first loop circuit includes a phase detector, a first counter, and a delay cell. The second loop circuit includes a phase generator, the phase detector, a second counter, and a duty correction circuit (DCC).