Memory Chip ECS Feedback Loop for DRAM Error Control
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Solution Overview
Problem
Existing storage systems, particularly dynamic random access memory (DRAM), face challenges in efficiently performing error check and scrub (ECS) operations, as current methods lack flexibility and real-time control based on actual ECS check results.
Innovation Solution
A storage system comprising a memory chip and a memory controller, where the memory chip performs ECS operations on its memory array, generates an ECS finish flag signal, and sends it to the memory controller. The memory controller then generates an ECS start flag signal to initiate a new ECS cycle, allowing for adjustable timing and processing based on check result information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional ECS operations are performed in DRAM, then data integrity is maintained, but the system lacks flexibility and real-time control based on actual ECS check results
Solution Approach 1:
The patent implements a feedback mechanism where the memory chip sends ECS finish flag signals and check result information to the memory controller, which then adjusts subsequent ECS operations based on the actual check results. This closed-loop feedback system enables real-time control and flexibility in ECS operations while maintaining data integrity through adaptive error correction strategies.
Solution Approach 2:
The patent introduces dynamic control of ECS operations by allowing the memory controller to adjust ECS timing and frequency based on actual error check results. The system transitions from static, fixed-interval ECS operations to dynamic, adaptive ECS scheduling, improving versatility while maintaining reliability through result-based adjustment.
2Reliability
If ECS operations are performed frequently to ensure data integrity, then error detection capability is improved, but system complexity and control difficulty increase
Solution Approach 1:
The memory chip autonomously performs ECS operations and generates check result information, reducing the control burden on the memory controller. The self-service mechanism handles error detection and reporting internally, simplifying the overall control process while maintaining strong error detection capability.
Solution Approach 2:
The patent segments the ECS control function into distinct components: the memory chip handles execution and result generation, while the memory controller handles scheduling and adjustment. This functional segmentation reduces control complexity by distributing responsibilities across system components.
3Reliability
If ECS operations are performed on all memory addresses, then comprehensive error coverage is achieved, but operation time and productivity are reduced
Solution Approach 1:
The patent implements targeted ECS operations by identifying and focusing error checking on specific memory regions or addresses that exhibit error patterns. Instead of uniformly checking all memory addresses, the system applies local quality control by concentrating ECS resources on problematic areas, achieving comprehensive error coverage where needed while improving overall operation speed.
Solution Approach 2:
The patent employs partial ECS action by performing error checks on selected memory addresses rather than all addresses in every ECS cycle. This partial action approach maintains adequate error coverage for critical regions while reducing the total operation time and improving productivity.
Data Source
AI summary
Provided are a storage system, a memory chip, and an error check and scrub method. The storage system includes a memory controller and a memory chip. The memory chip performs an error check and scrub ECS operation on a memory array; and sends a generated ECS finish flag signal to the memory controller after a current ECS operation is completed. The memory controller receives the ECS finish flag signal, and sends a generated ECS start flag signal to the memory chip based on the ECS finish flag signal, so that the memory chip enters a new ECS operation cycle.