Memory Chip Fast Read Mode Optimization
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Solution Overview
Problem
In NAND flash memory devices, the increasing number of memory cells connected to bit lines and the miniaturization of memory devices lead to longer read times due to reduced cell current and increased voltage application times, affecting the efficiency of data reading.
Innovation Solution
Implementing a memory chip with a memory controller that offers two read modes: a normal read mode and a fast read mode, where the fast read mode reduces the sense time and number of sensing operations, thereby decreasing the read time by optimizing the operation current and charging times of bit lines and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells connected to bit lines is increased to achieve high integration, then the integration capacity is improved, but the cell current is reduced and read time increases
Solution Approach 1:
The patent divides the memory cell array into multiple blocks, each block containing a subset of memory cells connected to bit lines. By segmenting the large array into smaller manageable blocks, the patent maintains high integration capacity while ensuring that each block's cell current remains sufficient for fast reading. The sense amplifier operates on selected blocks independently, resolving the contradiction between total integration and individual read speed.
2Volume of moving object
If memory devices are miniaturized to increase integration density, then the device size is reduced, but the voltage application time increases
Solution Approach 1:
The patent implements a pre-charge phase before the actual read operation, where bit lines and word lines are pre-charged to appropriate voltage levels. This preliminary action compensates for the increased capacitance effects in miniaturized devices, ensuring that when the read operation begins, the voltage application time is minimized. The pre-charge phase prepares the electrical environment in advance, offsetting the delays introduced by device miniaturization.
3Loss of time
If the sense time is reduced to increase reading speed, then the read time is decreased, but the data accuracy may be compromised
Solution Approach 1:
The patent employs a feedback mechanism where the sense amplifier continuously monitors the bit line voltage during the read operation and adjusts the sense time dynamically. If the voltage change indicates sufficient data detection, the sense operation terminates early, achieving fast reading. If not, the sense time is extended automatically. This feedback-controlled approach maintains data accuracy while maximizing reading speed by avoiding unnecessary sensing duration.
Data Source
AI summary
A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.